Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: A self-biased sense amplification circuit includes a local bit line, a reset unit, a main bit lie, a pre-amplifier, a data line, a sample reference unit, and a sense amplifier. The local bit line receives a cell current generated by a memory cell during a sense operation. The reset unit resets the local bit line to a first system voltage during a sample operation. The pre-amplifier generates a read current on the main bit line according to a voltage of the local bit line during the sample operation and the sense operation. The data line is coupled to the main bit line. The sample reference unit generates a first reference current and a second reference current during the sample operation, and generates the first reference current during the sense operation. The sense amplifier senses a voltage of the data line.

Abstract: A method for operating a plurality of memory cells includes performing a read operation to each of the plurality of memory cells. If at least one memory cell of the plurality of memory cells is determined to be in a programmed state, perform an erasing test operation to the at least one memory cell with an initial erase voltage being applied to the erase line, and perform a verification operation to the at least one memory cell. If the cell current is smaller than the reference current, generate an intermediate erase voltage by adding a step voltage to an erase voltage currently used, and perform the erasing test operation to the at least one memory cell with the intermediate erase voltage being applied to the erase line. Performing the verification operation to the at least one memory cell again.

Abstract: A memory cell of MRAM includes a PMOS transistor and a storage element. A first terminal of the PMOS transistor is connected with a first end of the memory cell. A control terminal of the PMOS transistor is connected with a second end of the memory cell. A first terminal of the storage element is connected with a second terminal of the PMOS transistor. A second terminal of the storage element is connected with a third end of the memory cell. During a write operation, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell. Consequently, the memory cell is in a first storage state.

Abstract: A random bit cell includes a selection transistor, a first P-type transistor, and a second P-type transistor. The selection transistor has a first terminal coupled to a source line, a second terminal coupled to a common node, and a control terminal coupled to a word line. The first P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a floating gate. The second P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a floating gate. During an enroll operation, one of the first P-type transistor and the second P-type transistor is programmed by channel hot electron injection.

Abstract: A reference voltage generator includes an output terminal, a current source, a reference circuit, a protection circuit, and a control circuit. The output terminal outputs a reference voltage. The current source is coupled to the output terminal, and generates a reference current. The reference circuit is coupled to the output terminal, and generates a reference voltage according to the reference current. The protection circuit is coupled to the output terminal, and adjusts a voltage of the output terminal to an operating voltage. The control circuit is coupled to the reference circuit and the protection circuit. The control circuit controls the reference circuit and the protection circuit according to a start signal.

Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.

Abstract: A random code generator includes an address Y decoder, an address X decoder, a PUF entropy pool, a processing circuit and an entropy key storage circuit. The address Y decoder includes plural Y control lines. The address Y decoder selectively activates the plural Y control lines according to a first address Y signal. The address X decoder includes plural X control lines. The address X decoder selectively activates the plural X control lines according to a first address X signal. The PUF entropy pool generates an output data according to the activated Y control lines and the activated X control lines. When the random code generator is in a normal working state, the processing circuit processes the output data into a random code according to at least one entropy key from the entropy key storage circuit.

Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by performing computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.

Abstract: A storage cell includes a selection circuit, a first memory transistor, and a second memory transistor. The selection circuit is coupled to a source line and a common node. When the selection circuit is turned on, the selection circuit forms an electrical connection between the source line and the common node. The first memory transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a control terminal coupled to a control line. The second memory transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a control terminal coupled to the control line. The first memory transistor and the second memory transistor are 2-dimension charge-trapping devices or 3-dimension charge-trapping devices.

Abstract: The communication system includes a communication buffer and a communication terminal. The communication buffer includes a physical unclonable function (PUF) device, and the communication buffer provides a security key generated by the PUF device. The communication terminal is coupled to the communication buffer, and transmits a mapping request to the communication buffer to ask for the security key. The communication terminal manipulates the transmission data with the security key to generate the encrypted data, and transmits the encrypted data to the communication buffer. The communication buffer further restores the transmission data from the encrypted data according to the security key.

Abstract: A true random number generation system includes a physical unclonable function (PUF) entropy device, a pseudo random number generator, and an encoding circuit. The PUF entropy device is used for generating a random number pool. The pseudo random number generator is used for generating a plurality of first number sequences. The encoding circuit is coupled to the PUF entropy device and the pseudo random number generator for generating a plurality of second number sequences according to the plurality of first number sequences and a plurality of third number sequences selected from the random number pool.

Abstract: An entanglement and recall system includes an antifuse-type PUF cell array and a processing circuit. The antifuse-type PUF cell array generates at least one key. The processing circuit is connected with the antifuse-type PUF cell array to receive the at least one key. While an entanglement action is performed, the processing circuit receives a plain text and the at least one key and generates a cipher text according to the plain text and the at least one key. While a recall action is performed, the processing circuit receives the cipher text and the at least one key and generates the plain text according to the cipher text and the at least one key.

Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.

Abstract: An integrated circuit includes a core circuit and a function lock circuit. The core circuit includes at least one function block circuit. The function lock circuit is coupled to the core circuit. The function lock circuit includes a random number source, an entanglement circuit, and a memory. The random number source is configured to generate a random code. The entanglement circuit is coupled to the random number source and the core circuit and configured to generate an unlocking code according to the random code and a command signal. The memory is coupled to the entanglement circuit and configured to store the unlocking code. The at least one function block circuit of the core circuit is determined to be locked/unlocked according to a presence of the unlocking code.

Abstract: A memory system includes a non-volatile memory block, a random bit block, and a sense amplifier. The non-volatile memory block includes a plurality of non-volatile memory cells for storing a plurality of bits of data. Each of the non-volatile memory cells includes a first storage transistor. The random bit block includes a plurality of random bit cells for providing a plurality of random bits. Each of the random bit cells includes a second storage transistor and a third storage transistor. The sense amplifier senses a first read current of a non-volatile memory cell during a read operation of the non-volatile memory cell and senses a second read current of a random bit cell during a read operation of the random bit cell. The first storage transistor, the second storage transistor, and the third storage transistor are storage transistors of the same type.

Abstract: An electrostatic discharge protection device is provided. A voltage selection circuit selects a voltage having a higher voltage value among a reference voltage and a voltage on a conductive path and supply the selected voltage to a RC latch self-feedback circuit, so that the RC latch self-feedback circuit ties a voltage of an input end of a RC control circuit when the electrostatic discharge does not occur, and disconnect a switch that conducts an electrostatic current.

Abstract: A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.

Abstract: A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.