Patents Assigned to Edge Technology
  • Publication number: 20060003577
    Abstract: To effectively reduce the dielectric constant of an interlayer insulation film including a low dielectric constant film of a porous structure, and easily realize a practical application of a semiconductor device having an ultrafine and highly reliable Damascene wiring structure. A first interlayer insulation film including a porous first low dielectric constant film is formed on a lower layer wiring, and a first side wall metal is formed on a side wall of a via hole arranged in the first low dielectric constant film, and thereafter a first etching stopper layer is etched and the lower layer wiring is exposed. Then, a via plug is embedded into the via hole. In the same manner, after a second side wall metal is arranged on a side wall of a trench in a second interlayer insulation film including a porous second low dielectric constant film, a second etching stopper layer is etched, and an upper layer wiring that connects to the via plug is formed.
    Type: Application
    Filed: January 19, 2005
    Publication date: January 5, 2006
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Shuji Sone
  • Publication number: 20050287811
    Abstract: A method of performing microfabrication using a hard mask in the manufacture of a semiconductor device having an interlayer dielectric (ILD) film made of low-dielectric constant, K, insulating material is provided. When treating a low-K dielectric film for use in semiconductor integrated circuitry and its underlying etching stopper film, a patterned resist film is used as a mask to etch a hard mask film. Subsequently, the resist pattern is subjected to stripping or “ashing” in the atmosphere of a mixture gas of hydrogen (H2) and helium (He) at a temperature higher than 200° C. under a pressure of about 1 Torr. With this procedure, microfabrication relying upon the hard mask less in facet is achievable during its subsequent etching of the low-K dielectric film, without damaging the hard mask film upon removal of the resist.
    Type: Application
    Filed: January 19, 2005
    Publication date: December 29, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Kazuaki Inukai
  • Publication number: 20050274948
    Abstract: A gate insulating film and a gate electrode are formed on a silicon substrate. The gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen. The fluorine concentration is high in the vicinity of an interface with the silicon substrate and progressively decreases with decreasing distance from the gate electrode. The nitrogen concentration is high in the vicinity of an interface with the gate electrode and progressively decreases with decreasing distance from the silicon substrate. The fluorine concentration in the vicinity of the interface with the silicon substrate is preferably 1×1019 cm?3 or more. The nitrogen concentration in the vicinity of the interface with the gate electrode is preferably 1×1020 cm?3 or more.
    Type: Application
    Filed: December 17, 2004
    Publication date: December 15, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Yasuyuki Tamura, Takaoki Sasaki
  • Publication number: 20050253269
    Abstract: A semiconductor device comprises a semiconductor layer; a stacked body; and an electrode pad provided on the stacked body. The stacked body is provided on the semiconductor layer and has a plurality of stacked layers. The electrode pad is provided on the stacked body. The stacked body has a subpad region that is located below the electrode pad and an extrapad region that is not located below the electrode pad, and any portion made of insulating material in the electrode subpad region except a contact plug layer directly above the semiconductor layer in the stacked body is surrounded by a metal interconnect having a closed structure in the same layer.
    Type: Application
    Filed: December 20, 2004
    Publication date: November 17, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Hiroshi Tsuda
  • Publication number: 20050249876
    Abstract: An atomic layer deposition (ALD) apparatus capable of forming a conformal ultrathin-film layer with enhanced step coverage is disclosed. The apparatus includes an ALD reactor supporting therein a wafer, and a main pipe coupled thereto for constant supply of a carrier gas. This pipe has two parallel branch pipes. Raw material sources are connected by three-way valves to one branch pipe through separate pipes, respectively. Similarly, oxidant/reducer sources are coupled by three-way valves to the other branch pipe via independent pipes. ALD works by introducing one reactant gas at a time into the reactor while being combined with the carrier gas. The gas is “chemisorped” onto the wafer surface, creating a monolayer deposited. During the supply of a presently selected material gas from its source to a corresponding branch pipe, this gas passes through its own pipe independently of the others. An ALD method is also disclosed.
    Type: Application
    Filed: January 14, 2005
    Publication date: November 10, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Takaaki Kawahara, Kazuyoshi Torii
  • Publication number: 20050205940
    Abstract: In a semiconductor device having a first transistor and a second transistor, the first transistor includes a first gate electrode composed of a first material having a first work function, and a first gate insulating film. The second transistor includes a second gate electrode composed of a second material having a second work function, and a second gate insulating film. The first gate insulating film includes a high-dielectric-constant film, and a first insulating film on the high-dielectric-constant film. In the second gate insulating film, after removing the first gate electrode, the first insulating film on the high-dielectric-constant film is removed.
    Type: Application
    Filed: December 6, 2004
    Publication date: September 22, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Fumio Ootsuka
  • Publication number: 20050205521
    Abstract: A wet etching apparatus comprises a stage for fixing a substrate having a major surface covered with a film to be etched, a rotation mechanism for rotating the stage, a rotation controller for controlling rotation operation by the rotation mechanism, an ultraviolet irradiation unit having a light source for irradiating a portion of the major surface of the substrate with ultraviolet radiation, and an etching solution supply unit for supplying etching solution to the major surface of the substrate. The entire surface of the substrate can be irradiated with the ultraviolet radiation by a rotation of the stage.
    Type: Application
    Filed: January 21, 2005
    Publication date: September 22, 2005
    Applicants: Semiconductor Leading Edge Technologies, Inc., Ushio Denki Kabushiki Kaisha
    Inventors: Satsohi Kume, Hiroshi Sugahara, Nobuyuki Hishinuma
  • Publication number: 20050208756
    Abstract: Disclosed is a method of removing resist preventing increase of dielectric constant of low permittivity insulating films and preventing remains of resist. Using a resist mask, a protection insulating film, a MSQ film, and a silicon oxide film composing an ILD are RIE dry etched sequentially, and a via is formed on the surface of a substrate for processing reaching the diffusion layer on the substrate for processing. Subsequent process consists of; removing a modified layer formed on the substrate for processing surface because of prior etching using plasma gas by plasma excitation of NH3 gas, and another etching for complete removal of the resist mask by irradiation of hydrogen active species created by hydrogen gas and inert gas, of which example is helium gas or argon gas.
    Type: Application
    Filed: February 9, 2005
    Publication date: September 22, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Atsushi Matsushita, Isao Matsumoto, Kazuaki Inukai, Hong Shin, Naofumi Ohashi, Shuji Sone, Kaori Misawa
  • Publication number: 20050199586
    Abstract: In resist removal using hydrogen gas, the specific dielectric constant of an insulating film of a low dielectric constant can be reduced and the resist removal speed can be increased. A wafer is loaded on a rotary table in a chamber, and hydrogen mixed gas is introduced into a discharge tube from a gas introduction port, and a ? wave is supplied into the discharge tube via a waveguide, and the mixed gas is excited by plasma, and a hydrogen active species is generated. And, a neutral radical (hydrogen radical) of hydrogen atoms or hydrogen molecules is introduced into the chamber from a gas transport pipe and a resist mask on the surface of the wafer is removed. Here, by a substrate heating system for heating the rotary table and controlling the temperature, the temperature of the wafer is set within the range from 200° C. to 400° C. The processed gas after resist removal is ejected from the chamber through a gas ejection port by an exhaust system.
    Type: Application
    Filed: February 9, 2005
    Publication date: September 15, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Atsushi Matsushita, Isao Matsumoto, Kazuaki Inukai, Hong Shin, Naofumi Ohashi, Shuji Sone, Kaori Misawa
  • Publication number: 20050199963
    Abstract: An element isolation dielectric film is formed around device regions in a silicon substrate. The device regions are an n-type diffusion region, a p-type diffusion region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric film includes a silicon oxide film and a hafnium silicate nitride film. The n-type gate electrode includes an n-type silicon film and a nickel silicide film, and the p-type gate electrode includes a nickel silicide film. The hafnium silicate nitride films are not on the sidewalls of the gate electrodes.
    Type: Application
    Filed: December 21, 2004
    Publication date: September 15, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Tomonori Aoyama
  • Publication number: 20050202323
    Abstract: A phase shift mask comprises a transparent substrate and a light shielding film. The transparent substrate has two regions that transmit exposure light. The exposure light transmitted through one region having a phase that is inverted in a recessed portion formed in the other region. The light shielding film shields the exposure light. The light shielding film is formed on the transparent substrate with a plurality of film thicknesses and has an edge that does not hang over the recessed portion.
    Type: Application
    Filed: December 28, 2004
    Publication date: September 15, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Kunio Watanabe
  • Publication number: 20050203721
    Abstract: The group creation part divides n ion particles into groups of a group G1, a group G2, . . . , and a group Gk. The individual area setting part sets an initial condition calculation area 1a, as an individual area of the group G1, and makes the calculation part calculate movement of the ion particle. Then, one by one, the individual area setting part sets an individual area of a group Gi+1, based on a range Rp, a dispersion ?L, etc. indicating a calculation result of an ion particle belonging to the group G1. Further, the individual area setting part implants an ion particle belonging to the group Gi+1 into the individual area of the group Gi+1 and makes the calculation part calculate movement of the implanted ion particle.
    Type: Application
    Filed: January 10, 2005
    Publication date: September 15, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Sanae Ito
  • Patent number: 6943899
    Abstract: A substrate-container measuring device has a kinematic plate 10 having securing pins 12 provided at positions defined by the SEMI standards. There is provided an optical distance-measuring sensor 14, in which a relative position between the optical distance-measuring sensor 14 and the kinematic plate 10 is fixed. A substrate-container measuring jig 20 is placed on the kinematic plate 10. The substrate-container measuring jig 20 has a base plate 22 to be placed on the kinematic plate 10, and a slide plate 24 that is slidable over the base plate 22. The base plate 22 has a group of grooves which uniquely determine a relative position between the base plate 22 and the kinematic plate 10 as a result of being fitted with the corresponding securing pins 12.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: September 13, 2005
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Hisaharu Seita
  • Publication number: 20050196977
    Abstract: A method of forming a silicon nitride film comprises: forming a silicon nitride film by applying first gas containing silicon and nitrogen and second gas containing nitrogen and hydrogen to catalyst heated in a reduced pressure atmosphere. A method of manufacturing a semiconductor device comprising the steps of: forming a silicon nitride film by the method as claimed in claim 1 on a substrate having the semiconductor layer, a gate insulation film selectively provided on a principal surface of the semiconductor layer, and a gate electrode provided on the gate insulation film; and removing the silicon nitride film on the semiconductor layer and the gate electrode and leaving a sidewall comprising the silicon nitride film on a side surface of the gate insulation film and the gate electrode by etching the silicon nitride film in a direction generally normal to the principal surface of the semiconductor layer.
    Type: Application
    Filed: February 15, 2005
    Publication date: September 8, 2005
    Applicants: Semiconductor Leading Edge Technologies, Inc., ULVAC, Inc.
    Inventors: Tsuyoshi Saito, Hiromi Itoh, Makiko Kitazoe
  • Patent number: 6938961
    Abstract: An improved buster point assembly is disclosed. The improved buster point assembly has an elongated shaft attached to a replaceable tip. The replaceable tip includes a working end and a connecting end, the connecting end has a chamber for receiving a distal end of the elongated shaft.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: September 6, 2005
    Assignee: Cutting Edge Technologies, LLC
    Inventor: Gilbert R. Broom
  • Publication number: 20050191847
    Abstract: A heat treatment is performed to an insulating film composition, formed on a semiconductor substrates at a temperature of 350° C. in an inert gas ambient to form a non-porous insulating film. Next, dry etching is performed using a resist pattern as a mask to form a trench in the non-porous insulating film, ashing is performed to remove the resist pattern, and the surface of the semiconductor substrate is cleaned. Thereafter, a second heat treatment is performed for the non-porous insulating film to form a porous insulating film. Since the second heat treatment is performed in an oxidizing-gas atmosphere, the pore-generating material can be removed at a temperature lower than the temperature of conventional methods to form an insulating film having a low dielectric constant.
    Type: Application
    Filed: December 14, 2004
    Publication date: September 1, 2005
    Applicant: Semiconductor Leading edge Technologies, Inc.
    Inventors: Kaori Misawa, Naofumi Ohashi
  • Publication number: 20050191850
    Abstract: A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film as a mask, the resist film and the antireflective film are removed by ashing. Thereafter, the first insulating film is dry etched, using the third insulating film as a mask, to form a wiring trench extending to the lower-layer wiring. The dry etching of the third insulating film and the second insulating film is performed using a gas containing fluorine at a pressure of 0.1 Pa to 4 Pa. Ashing is preferably performed using at least one of hydrogen and an inert gas.
    Type: Application
    Filed: December 3, 2004
    Publication date: September 1, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Eiichi Soda
  • Publication number: 20050184255
    Abstract: An ion implantation simulator that computes an ion density distribution at high speed and with high accuracy based on a beam dispersion phenomenon in an ion implantation process. The ion implantation simulator is provided with the beam dispersion approximate function storage section 121, which stores a beam dispersion approximate function that is obtained through approximation of ion beam dispersion by using a predetermined function; a beam intensity computing section 131, which computes an area surface beam intensity that indicates an intensity of the ion beam on a surface of an implanted area by using the beam dispersion approximate function; and an ion density distribution computing section 132, which computes the density distribution of the ion, which is implanted by the ion beam into the device through the surface of the implanted area, by using the area surface beam intensity.
    Type: Application
    Filed: January 27, 2005
    Publication date: August 25, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Hirotaka Amakawa
  • Publication number: 20050179134
    Abstract: A semiconductor device having a first wiring layer including first wirings on a substrate, a contact layer on the first wiring layer and including contacts connected to the first wirings, and a second wiring layer on the contact layer and including second wirings connected to the contacts. Contact pitch is larger than the minimum wiring pitch of the first wirings or the minimum wiring pitch of the second wirings.
    Type: Application
    Filed: December 3, 2004
    Publication date: August 18, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Yoshihisa Matsubara
  • Publication number: 20050181576
    Abstract: A method of forming an inorganic porous film comprises applying, to a support, an inorganic material composition including a mixture of a silicon oxide precursor containing at least one hydrolyzable silane compound and a pore-generating material, thereby forming a film, drying the film, contacting the film after the drying with a supercritical fluid to remove the pore-generating material; and baking the film after the removal of the pore-generating material.
    Type: Application
    Filed: May 29, 2003
    Publication date: August 18, 2005
    Applicant: Semiconductor Leading edge Technologies, Inc
    Inventors: Shinichi Ogawa, Takashi Nasuno, Naruhiko Kaji