Patents Assigned to Edge Technology
  • Semiconductor device having bonding pad above low-k dielectric film and manufacturing method therefor
    Publication number: 20050173806
    Abstract: A semiconductor device comprises, a protective element on a substrate; a low-k dielectric film opposite the protective element and having mechanical strength smaller than a silicon oxide film; a mesh wiring opposite the protective element and in the low-k dielectric film, the mesh wiring including power supply wirings and ground wirings arranged in a mesh, the mesh wiring being electrically connected to the protective element; a silicon oxide film on the mesh wiring and the low-k dielectric film; and a bonding pad on the silicon oxide film and opposite the mesh wiring.
    Type: Application
    Filed: December 13, 2004
    Publication date: August 11, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Yoshihisa Matsubara
  • Method for manufacturing semiconductor device
    Publication number: 20050170102
    Abstract: A method for manufacturing a semiconductor device comprises: exposing a surface of a substrate to plasma; and forming an insulating film containing a low dielectric constant material on the surface of the substrate. A method for manufacturing a semiconductor device comprises: forming a modified layer by exposing a surface of a substrate to plasma; and forming an insulating film containing a low dielectric constant material on the modified layer. A method for manufacturing a semiconductor device comprises: forming an adhesion enhancement layer on a substrate; exposing a surface of the adhesion enhancement layer to plasma; and forming a first insulating film on the adhesion enhancement layer.
    Type: Application
    Filed: January 18, 2005
    Publication date: August 4, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Isao Matsumoto, Naofumi Ohashi, Kaori Misawa, Shuji Sone
  • Multilayered wiring structure, method of forming buried wiring, semiconductor device, method of manufacturing semiconductor device, semiconductor mounted device, and method of manufacturing semiconductor mounted device
    Publication number: 20050170641
    Abstract: A method of forming a buried wiring in a low-k dielectric film, includes: forming a low-k dielectric film having a dielectric constant of 3 or less on an underlayer; removing the low-k dielectric film by a first width from an edge of the underlayer; forming a cap film on the low-k dielectric film, after removing the low-k dielectric film by the first width; forming a groove in the cap film and the low-k dielectric film; forming a conductive film in the groove and on the cap film; removing the conductive film by a second width, different from the first width by 1 mm or more, from the edge of the underlayer; and polishing unnecessary portions of the conductive film on the cap film, after removing the conductive film by the second width.
    Type: Application
    Filed: December 20, 2004
    Publication date: August 4, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Seiichi Kondo, Kaori Misawa
  • Semiconductor apparatus and manufacturing method of the same
    Publication number: 20050167767
    Abstract: A semiconductor apparatus comprises a first semiconductor device and a second semiconductor device. The first semiconductor device includes: a semiconductor layer having a p-type channel area; an n-type source area, and an n-type drain area; a first gate insulating film provided on the p-type channel area; and a first gate electrode provided on the first gate insulating film containing a first metallic element and nitrogen. The second semiconductor device includes: a semiconductor layer having an n-type channel area, a p-type source area, and a p-type drain area; a second gate insulating film provided on the n-type channel area; and a second gate electrode provided on the second gate insulating film containing a second metallic element and nitrogen. A nitrogen content of the second gate electrode is higher than a nitrogen content of the first gate electrode.
    Type: Application
    Filed: January 28, 2005
    Publication date: August 4, 2005
    Applicant: Semiconductor Leading Edge Technologies , Inc.
    Inventor: Yasushi Akasaka
  • Semiconductor device and method of manufacturing same
    Publication number: 20050167788
    Abstract: A semiconductor device comprises: a substrate; a first film provided on the substrate; an insulation layer made of low-k material provided on the first film; a protection layer provided on a sidewall of a hole penetrating through the insulation layer and the first film to the substrate to cover the insulation layer, and a conducting portion filling the hole. The protection layer is more compact than the low-k material.
    Type: Application
    Filed: December 29, 2004
    Publication date: August 4, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Isao Matsumoto
  • Method of manufacturing a thin film battery
    Patent number: 6921464
    Abstract: In a method of manufacturing a thin film battery in a chamber, a target comprising LiCoO2 is provided on a magnetron cathode in the chamber, and a substrate is placed facing the target. A process gas is introduced into the chamber and the process gas is energized to form a plasma to sputter the target to deposit LiCoO2 on the substrate. An ion flux of from about 0.1 to about 5 mA/cm2 is delivered from the plasma to the substrate to enhance the crystallinity of the deposited LiCoO2 material on the substrate. The process gas is exhausted from the chamber. The target can also be made of other materials.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: July 26, 2005
    Assignee: Front Edge Technology
    Inventors: Victor Krasnov, Kai-Wei Nieh, Su-Jen Ting
  • Method for manufacturing semiconductor device
    Publication number: 20050153536
    Abstract: A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film as a mask, the resist film and the antireflective film are removed by ashing. Thereafter, the first insulating film is dry etched, using the third insulating film as a mask, to form a wiring trench extending to the lower-layer wiring. Dry etching uses a fluorocarbon-based gas to which at least one of hydrogen and an inert gas is added. Ashing is performed using at least one of hydrogen and an inert gas.
    Type: Application
    Filed: December 3, 2004
    Publication date: July 14, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Eiichi Soda
  • Mass-production transfer support system and semiconductor manufacturing system
    Publication number: 20050143853
    Abstract: A mass-production transfer support system has a mass-production transfer source managing computer for managing information generated in a trial-production process of a semiconductor device and a mass-production transfer destination managing computer for managing a mass-production process of the semiconductor device.
    Type: Application
    Filed: December 27, 2004
    Publication date: June 30, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Hiroyuki Akimori, Yasushi Ohyama, Hidetaka Nishimura, Shigeru Kobayashi
  • Structure of test element group wiring and semiconductor substrate
    Publication number: 20050139826
    Abstract: A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the electrode, includes dummy wirings electrically isolated from the electrode and having a portion of the same shape as the real wiring. The dummy wirings are disposed at a predetermined constant distance adjacent to the real wirings or to each other, so that the wiring rate of the real wiring relaxes the concentration difference of patterns. The distance between the real wirings is sufficient to perform pattern analysis using the OBIRCH method.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 30, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Takashi Nasuno, Hiroshi Tsuda
  • Semiconductor device method for manufacturing the same, apparatus for forming film, and method for forming high-dielectric-constant film
    Publication number: 20050139937
    Abstract: A semiconductor device having a gate electrode on a silicon substrate via a gate insulating film is formed by laminating the gate insulating film with a silicon oxide film, formed on the silicon substrate, an Hf silicate film is formed on the silicon oxide film, and a nitrogen-containing Hf silicate film formed on the Hf silicate film, and containing Hf in a peak concentration in a range from one atomic % to thirty atomic %, and nitrogen in a peak concentration in a range from ten atomic % to thirty atomic %.
    Type: Application
    Filed: March 30, 2004
    Publication date: June 30, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Satoshi Kamiyama, Tsunetoshi Arikado
  • Method of fabricating a semiconductor device having metal wiring
    Publication number: 20050136644
    Abstract: A method of fabricating a semiconductor device includes forming a metal wire on a substrate, forming an interlayer insulating film on the metal wire, forming a resist pattern on the interlayer insulating film, selectively etching the interlayer film to form a trench or via-hole in the interlayer insulating film and reaching the metal wire, and ashing, using a reducing gas, to remove the resist pattern.
    Type: Application
    Filed: December 20, 2004
    Publication date: June 23, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Kazuaki Inukai, Atsushi Matsushita
  • Catalytic CVD equipment, method for catalytic CVD, and method for manufacturing semiconductor device
    Publication number: 20050132961
    Abstract: A catalytic CVD equipment comprises: a vacuum chamber; a stage; a first catalyzer; and a second catalyzer. The stage holds a substrate in the vacuum chamber. The first catalyzer is provided in the vacuum chamber and has a bar member arranged substantially in parallel to a major surface of the substrate. The second catalyzer is provided in the vacuum chamber, and has a bar member arranged at a tilted angle to the major surface of the substrate. A thin film is deposited on the substrate held on the stage by introducing a source gas, by heating the first and the second catalyzer, and by decomposing the gas in the vacuum chamber under a low pressure.
    Type: Application
    Filed: December 16, 2004
    Publication date: June 23, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Tsuyoshi Saito
  • Semiconductor device and its manufacturing method
    Publication number: 20050121786
    Abstract: A semiconductor device comprises a semiconductor substrate and an interlayer interconnection structure provided on the semiconductor substrate. The interlayer interconnection structure includes a porous insulation film and a conductive part of a conductive material containing a metal as a major component. A volume occupation ratio of pores of a diameter greater than 0.6 nanometers is less than 30% in the porous insulation film.
    Type: Application
    Filed: November 3, 2004
    Publication date: June 9, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Akira Furuya, Nobuyuki Ohtsuka, Shinichi Ogawa, Hiroshi Okamura
  • Photomask, and method for forming pattern
    Publication number: 20050100799
    Abstract: In an exposure step, a combination of a first photomask and a second mask is used. The first mask has a real pattern corresponding to the pattern actually formed on the film to be processed, and a dummy pattern added for controlling pattern pitch in the first photomask within a prescribed range; and the second photomask has a pattern isolating a real-pattern-formed region from a dummy-pattern-formed region. In forming the pattern, after forming a film to be processed on a substrate, a first mask is formed on the film to be processed, by lithography, using the first photomask, and a second mask is formed on the film to be processed, by lithography, using the second photomask. Thereafter, the film to be processed is etched and removed using the first and second masks as masks to form the pattern.
    Type: Application
    Filed: October 28, 2004
    Publication date: May 12, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Takuya Hagiwara
  • Method for manufacturing semiconductor device
    Publication number: 20050101157
    Abstract: An insulating-film composition containing an insulating-film precursor and a pore-generating material is applied onto a surface of a semiconductor substrate, and a first heat treatment is performed to polymerize the insulating-film precursor without vaporizing the pore-generating material, to form a non-porous insulating film. Next, a resist pattern is formed on the non-porous insulating film, and dry etching is performed, using the resist pattern as a mask, to form a trench in the non-porous insulating film. After removing the resist pattern by ashing, the surface of the semiconductor substrate is cleaned. Next, a second heat treatment is performed to remove the pore-generating material from the non-porous insulating film and to form a porous insulating film. Thereafter, a copper layer is deposited in the trench on a barrier-metal film to form copper wiring.
    Type: Application
    Filed: November 4, 2004
    Publication date: May 12, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Takashi Yunogami, Kaori Misawa
  • Exposure method
    Publication number: 20050095539
    Abstract: An exposure method includes forming a resist film on a substrate to be processed, forming a top anti-reflection coating on the resist film, and irradiating the resist film with exposure light through the top anti-reflection coating. Forming the top anti-reflection coating includes adjusting refractive index and thickness of the top anti-reflection coating to increase a ratio of s-polarized light to p-polarized light in the exposure light entering the resist film.
    Type: Application
    Filed: October 27, 2004
    Publication date: May 5, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Kouichirou Tsujita
  • Semiconductor device and method for manufacturing semiconductor device
    Publication number: 20050082605
    Abstract: A gate insulating film is formed in a first region and a second region of a substrate, a first metallic film is formed on the gate insulating film in one of the first region or the second region, and a second metallic film is formed on each of the first and second regions. Furthermore, a protective film is formed on the second metallic film, and the protective film and the metallic film are patterned to the pattern of the gate electrode. Next, a first sidewall is formed on the side of a gate electrode. Then, impurities producing first and second conductivity types are implanted into the surface of the substrate in respective regions, using the first sidewalls and the gate electrodes as masks to form a first impurity-diffused region, and impurities producing second and first conductivity types are implanted to form an impurity diffusion preventing layer.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 21, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Yasushi Akasaka
  • Method of fabricating multilayer interconnect wiring structure having low dielectric constant insulator film with enhanced adhesivity
    Publication number: 20050085097
    Abstract: A method for fabricating a high density semiconductor integrated circuit device with a multilayer interconnect wiring structure is disclosed. This structure has a low-dielectric constant insulator film including an organic thin-film with its dielectric constant ranging from about 2.0 to about 2.4. To fabricate the multilayer wiring structure, a substrate with an inorganic film for use as an underlayer dielectric film is prepared. Then, apply plasma processing, such as plasma-assisted chemical vapor-phase growth, to a top surface of the inorganic underlayer dielectric film in environment that contains therein organic silane-based chemical compounds, thereby to form on the inorganic film surface a hydrophobic surface layer with a contact angle with water being 50° or higher. Next, form on the plasma-processed hydrophobic surface an organic film including a fluorinated aromatic carbon hydride polymer film.
    Type: Application
    Filed: August 27, 2004
    Publication date: April 21, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Naruhiko Kaji, Katsumi Yoneda
  • Apparatus and method of cleaning a substrate
    Patent number: 6880563
    Abstract: A cleaning apparatus is provided with a processing bath to be filled with a cleaning chemical, an ultrasonic oscillator, and a retainer for holding a substrate to be immersed into a cleaning chemical. The front surface of the substrate is cleaned while ultrasonic waves are radiated from the ultrasonic oscillator onto the back surface of the substrate.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: April 19, 2005
    Assignee: Semiconductor Leading Edge Technologies, Inc
    Inventor: Satoshi Kume
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 6881657
    Abstract: In a method for forming a semiconductor device, the major surface of a substrate is separated into a first element region for forming a first field-effect transistor and a second element region for forming a second field-effect transistor. A silicon nitride film is formed in each of the first and second element regions. Thereafter, the silicon nitride film formed in the second element region is removed, and the substrate is subjected to heat treatment in an ambient that contains nitrogen oxide. Thereby, the silicon nitride film in the first element region is oxidized to form an oxynitride film, and a silicon oxynitride film is formed in the second element region. Thereafter, a high-dielectric-constant film is formed on the silicon oxynitride films in each of the first and second element regions.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: April 19, 2005
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Kazuyoshi Torii, Riichirou Mitsuhashi, Atsushi Horiuchi