Patents Assigned to Edge Technology
  • Wafer edge exposure apparatus, and wafer edge exposure method
    Patent number: 6875971
    Abstract: A wafer edge exposure apparatus is provided with an optical section for radiating exposure light onto the edge of a semiconductor wafer. The optical section is provided with a focus sensor for sensing a distance from the lower end of the optical section to the edge of the semiconductor wafer. There is provided a position control mechanism for moving the optical section vertically on the basis of a value detected by the focus sensor such that the distance matches a focal distance of the optical section.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: April 5, 2005
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Jeong Yeal Kim
  • Method for manufacturing semiconductor device
    Publication number: 20050070081
    Abstract: A mask layer having an opening is formed on a semiconductor substrate. Next, oxygen ions and a first impurity are implanted into the semiconductor substrate using the mask layer as a mask. Then, the mask layer is removed. Next, the oxygen ions are heat treated to react and form an oxide film on the region where the first impurity has been implanted. Then, the oxide film is removed to form a depression in the semiconductor substrate. Next, a gate insulating film and a gate electrode are formed on the depression. Then a second impurity is implanted into the surface of the semiconductor substrate to form a source/drain. An impurity lighter than the oxygen ions and the second impurity is used as the first impurity.
    Type: Application
    Filed: August 18, 2004
    Publication date: March 31, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Kiyoshi Shibata
  • Method of manufacturing semiconductor device
    Publication number: 20050064699
    Abstract: A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.
    Type: Application
    Filed: September 15, 2004
    Publication date: March 24, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Seiichi Kondo, Kaori Misawa, Shunichi Tokitoh, Takashi Nasuno
  • Semiconductor device and manufacturing method therefor
    Publication number: 20050051845
    Abstract: A gate electrode in an NMOS region is one of intrinsic silicon and a material having a work function equivalent to that of intrinsic silicon, and a material having a work function smaller than that of intrinsic silicon. A gate electrode in a PMOS region is one of intrinsic silicon and a material having a work function equivalent to that of intrinsic silicon, and a material having a work function larger than that of intrinsic silicon. Further, a source/drain region in the NMOS region includes a silicide layer of a material having a work function smaller than that of intrinsic silicon, and a source/drain region in the PMOS region includes a silicide layer of a material having a work function larger than that of intrinsic silicon.
    Type: Application
    Filed: August 4, 2004
    Publication date: March 10, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Yoshikazu Nakagawa, Naoki Izumi
  • Semiconductor device
    Publication number: 20050051857
    Abstract: A semiconductor device of the present invention comprises: a silicon substrate; a gate insulating film on the silicon substrate; and a gate electrode on the gate insulating film, wherein the gate insulating film includes: a first insulating film; a second insulating film on the first insulating film; and a metal nitride film on the second insulating film. The metal nitride film may be either AlN or Hf3N4. The metal nitride film may include nitrides of two or more different metals.
    Type: Application
    Filed: July 30, 2004
    Publication date: March 10, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima
  • Sputter deposition of lithium phosphorous oxynitride material
    Patent number: 6863699
    Abstract: A method of depositing lithium phosphorus oxynitride on a substrate, the method comprising loading a substrate into a vacuum chamber having a target comprising lithium phosphate, introducing a process gas comprising nitrogen into the chamber and maintaining the gas at a pressure of less than about 15 mTorr; and forming a plasma of the process gas in the chamber to deposit lithium phosphorous oxynitride on the substrate.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: March 8, 2005
    Assignee: Front Edge Technology, Inc.
    Inventors: Victor Krasnov, Kai-Wei Nieh, Su-Jen Ting, Paul Tang, Fan-Hsiu Chang, Chun-Ting Lin
  • Method for manufacturing semiconductor device and semiconductor device
    Publication number: 20050045967
    Abstract: A gate insulating film having an insulating film that contains at least nitrogen is formed on a substrate, and the gate insulating film is subjected to heat treatment for about 500 milliseconds or less using a flash lamp. Thereafter, a gate electrode is formed on the gate insulating film. Specifically, for example, a laminated film of SiO2 and SixN(1-x), a laminated film of SiO2, HfSiO, and SixN(1-x), or the like, is formed in forming the gate insulating film.
    Type: Application
    Filed: August 12, 2004
    Publication date: March 3, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Takaoki Sasaki, Takeshi Hoshi
  • Semiconductor device and method for manufacturing the same
    Publication number: 20050045970
    Abstract: A gate insulating film on a silicon substrate includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
    Type: Application
    Filed: August 9, 2004
    Publication date: March 3, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Tsunetoshi Arikado, Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima, Seiichi Miyazaki
  • Semiconductor device with silicon-germanium gate electrode and method for manufacturing thereof
    Publication number: 20050045938
    Abstract: A semiconductor includes a gate electrode having a SiGe film on a a gate dielectric film that is on a silicon substrate. The gate dielectric film includes an underlying interfacial layer on the substrate, and a high-k dielectric film having higher dielectric constant than the underlying interfacial layer. The gate electrode includes a seed Si film on the high-k dielectric film and a SiGe film formed on the seed Si film. The seed Si film has a thickness of 0.1 nm or more and smaller than 5 nm.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 3, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Akiyoshi Mutou, Hiroshi Ohji
  • Method for manufacturing semiconductor device
    Publication number: 20050048774
    Abstract: After forming a gate insulating film and a gate electrode on a substrate, ion implantation is performed to form a doped region. Thereafter, ions are implanted in the doped region and the gate electrode to form an amorphous layer on the doped region and the gate electrode. The amorphous layer is subjected to heat treatment at temperatures of 550° C. to 650° C. and recrystallized. Thereafter, a material film is formed for forming a silicide layer, at least on the doped region and the gate electrode, and heat treatment is performed so the Si of the doped region and the gate electrode reacts with said material film to form a silicide layer. Furthermore, the material film that has not reacted is removed. The thickness of the amorphous layer formed is substantially identical to the thickness of the silicide layer.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 3, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Hiroshi Kitajima
  • Semiconductor device and manufacturing method therefor
    Publication number: 20050048728
    Abstract: A first insulating film is formed on a base substrate, then a second insulating film is formed on the first insulating film, the second insulating film having a relative permittivity higher than that of the first insulating film. A gate electrode is formed on the second insulating film. The second insulating film forming includes first to sixth steps, and a cycle consisting of the first to sixth steps is repeated.
    Type: Application
    Filed: August 13, 2004
    Publication date: March 3, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Takaaki Kawahara
  • Method of observation by transmission electron microscopy
    Publication number: 20050042781
    Abstract: A method for observing defect in an amorphous material by transmission electron microscopy is disclosed. The method comprises the steps of: incident electron beam into the amorphous material; eliminating a generated diffraction wave to form an image only by a transmission wave coming through the amorphous material; and observing the image under an under-focus condition. A method for respectively observing an amorphous material and a crystalline material in a composite material containing both of the amorphous material and the crystalline material by transmission electron microscopy is also disclosed.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 24, 2005
    Applicants: Semiconductor Leading Edge Technologies, Inc., NISSAN ARC, Ltd.
    Inventors: Shinichi Ogawa, Yasuhide Inoue, Junichi Shimanuki, Hirotaro Mori
  • Semiconductor device and method for manufacturing semiconductor device
    Publication number: 20050014352
    Abstract: In a method for forming a semiconductor device, the major surface of a substrate is separated into a first element region for forming a first field-effect transistor and a second element region for forming a second field-effect transistor. A silicon nitride film is formed in each of the first and second element regions. Thereafter, the silicon nitride film formed in the second element region is removed, and the substrate is subjected to heat treatment in an ambient that contains nitrogen oxide. Thereby, the silicon nitride film in the first element region is oxidized to form an oxynitride film, and a silicon oxynitride film is formed in the second element region. Thereafter, a high-dielectric-constant film is formed on the silicon oxynitride films in each of the first and second element regions.
    Type: Application
    Filed: July 13, 2004
    Publication date: January 20, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Kazuyoshi Torii, Riichirou Mitsuhashi, Atsushi Horiuchi
  • Semiconductor device having a damascene-type gate or a replacing-type gate and method of manufacturing the same
    Publication number: 20050001267
    Abstract: A semiconductor device includes semiconductor elements and at least one dummy pattern. Each or at least some of the semiconductor elements has a Damascene gate structure or a replacing gate structure and is located in element-forming regions. In addition, at least a dummy pattern is located in a region different from the element-forming regions. The dummy pattern may have a semiconductor element structure of the same or different kind from the Damascene gate structure or replacing gate structure. The dummy pattern may be a pattern of an insulating film, an interface transistor, or an analog circuit capacitor electrode instead of the dummy gate.
    Type: Application
    Filed: June 9, 2004
    Publication date: January 6, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Kazuhiro Miyagawa, Mitsuo Yasuhira, Yasushi Akasaka, Isamu Nishimura
  • Method for manufacturing semiconductor device
    Publication number: 20040259381
    Abstract: In a method for manufacturing a semiconductor device, an insulating film having pores is formed on a substrate, and an opening is formed in the insulating film. Thereafter, a material gas supplying Si or C is supplied to the insulating film. Thereby, deficient elements, such as Si or C, are supplied to the insulating film. Thereafter, in the opening, including a barrier metal, is filled with a conductive member to form a wiring structure.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 23, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Nobuyuki Ohtsuka, Akira Furuya, Shinichi Ogawa, Hiroshi Okamura
  • Method for manufacturing semiconductor device
    Publication number: 20040253790
    Abstract: In a method for manufacturing a semiconductor device, a gate insulating film and a gate electrode are first formed on a substrate. Next, Ge ions, Si ions, or the like are implanted to make the surface of the substrate amorphous, using the gate electrode as a mask. Thereafter, impurities such as B ions or the like, for forming a doped region, are implanted into the amorphous area of the substrate, using the gate electrode as a mask. Furthermore, the doped region is irradiated with visible light for a short period of time.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 16, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Fumio Ootsuka
  • Method for manufacturing semiconductor device
    Publication number: 20040248395
    Abstract: In a method for manufacturing a semiconductor device having a multi-layer insulating film, a first insulating film is formed as one layer of the multi-layer insulating film, and a plasma treatment is performed on the surface of the first insulating film in an ambient of helium and argon, containing 5 to 31% Ar. After the plasma treatment, a second insulating film, different from the first insulating film, is formed on the first insulating film as another layer of the multi-layer insulating film.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 9, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Katsumi Yoneda, Toru Yoshie
  • Semiconductor device with silicon-germanium gate electrode and method for manufacturing thereof
    Publication number: 20040238895
    Abstract: A SiO2 film serving as a gate dielectric film is formed on a silicon substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film of a thickness of 50 nm or less is formed on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film of a thickness of 0.5 nm to 5 nm is continuously formed on the thin SiGe film at the same temperature.
    Type: Application
    Filed: May 7, 2004
    Publication date: December 2, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Akiyoshi Mutou
  • Method for manufacturing semiconductor device
    Publication number: 20040235293
    Abstract: After forming a stopper film on a semiconductor substrate having a copper wiring layer therein, an interlayer insulating film made of a low dielectric constant material is formed on the stopper film. Then, after forming a capping film on the interlayer insulating film, a resist film having a predetermined pattern is formed on the capping film. The capping film and the interlayer insulating film are etched using the resist film as a mask to form an opening reaching the stopper film. After that, the stopper film exposed by the opening is etched, with the resist film left in place, to form a via hole. Then, the resist film is removed by ashing.
    Type: Application
    Filed: May 20, 2004
    Publication date: November 25, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Kazuaki Inukai, Atsushi Matsushita
  • Load port, wafer processing apparatus, and method of replacing atmosphere
    Patent number: 6817822
    Abstract: Atmosphere inside a wafer carrier is purged through an open face of the wafer carrier, in the state where a carrier door constituting a face of the wafer carrier is opened by a load port door. Purging is carried out by partitioning a mini-environment with an upper wall surface, a lower wall surface, and an EFEM door into a predetermined space adjacent to the open face, by discharging gas from the predetermined space through an exhaust opening, and by supplying an inert gas or a dry air from a gas supply port into the predetermined space.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: November 16, 2004
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Kenji Tokunaga