Abstract: A power outlet, and associated method, for an electrical power supply strip. The power outlet includes a housing, an electrical connection for receiving first electrical power type, electrical components to change the first electrical power type to a second electrical power type, and a connection interface to supplying the second electrical power type. The power outlet housing has a body with a shape that corresponds to a shaped aperture of a main housing of the strip. A front portion of the power outlet housing is larger than the shaped aperture. An elastically deformable arm extends from the body and deforms as the arm passes through the shaped aperture of the main housing. An engagement portion of the arm retains the power outlet housing relative to the main housing.

Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

Abstract: A semiconductor chip includes a first electrode connected to a gate of a power device, a second electrode connected to an emitter or a source of the power device, a third electrode, and a gate protection element. The gate protection element includes a first node and a second node, and a plurality of stages of p-n junctions formed between the first node and the second node. When one of the first electrode and the second electrode is a target electrode and the other is a non-target electrode, and the first node is connected to the third electrode and the second node is connected to the target electrode. Then, the first electrode, the second electrode, the third electrode and the gate protection element are formed in the same semiconductor chip.

Abstract: A semiconductor device includes: a first semiconductor chip mounted on a chip mounting portion via a first bonding material; and a second semiconductor chip mounted on the first semiconductor chip. Here, the first semiconductor chip has: a protective film located in an uppermost layer; and a first pad electrode exposed from the protective film at an inside of a first opening portion of the protective film. Also, the second semiconductor chip is mounted on a conductive material, which is arranged on the first pad electrode of the first semiconductor chip, via a second bonding material of an insulative property.

Abstract: A jitter cancellation circuit includes a clock buffer and a current control unit. The clock buffer inputs a clock outputted from a clock propagation element driven by a power supply voltage. Further, the clock buffer decreases with respect to a power supply voltage according to an increase in an operating current, while giving a delay time increased according to a decrease in the operating current to output the clock. The current control unit is configured to increase/decrease the operating current of the clock buffer in an opposite phase of a fluctuation component of the power supply voltage.

Abstract: A semiconductor device includes a first data line, a second data line, and a memory cell connected to the first data line and the second data line. The memory cell includes a plurality of switches, a first data holding circuit, a second data holding circuit, a third data holding circuit, a fourth data holding circuit, and an input line. A characteristic value of the memory cell is changeable by controlling the switch connected to the first data line among the plurality of switches based on a value held by the third data holding circuit and by controlling the switch connected to the second data line among the plurality of switches based on a value held by the fourth data holding circuit.

Abstract: A second memory has n banks accessible in parallel, and stores pixel data. An input DMA controller respectively transfers the pixel data stored in the second memory to n multiply-accumulate units by using n input channels. A sequence controller controls the input DMA controller so as to cause a first input channel to transfer the pixel data in a first pixel space of the input bank to a first multiply-accumulate unit and cause a second input channel to transfer the pixel data in a second pixel space of the same input bank to a second multiply-accumulate unit.

Abstract: A switching charger for accurately sensing a small current is provided. First terminals of first transistors and a second transistor are coupled to a system voltage. Second terminals of the first transistors and a first input terminal of an operational amplifier are connected to a battery. A first terminal of a third transistor is connected to a second terminal of the second transistor and a second input terminal of the operational amplifier. A control terminal of the third transistor is connected to an output terminal of the operational amplifier. A first terminal of a fourth transistor is connected to a second terminal of the third transistor. First terminals of fifth transistors are coupled to an input voltage. Control terminals of the first transistors and the fifth transistors are connected to a control circuit. First terminals of sixth transistors are respectively connected to second terminals of the fifth transistors.

Abstract: A relay control device controls an operation of a relay circuit, which is disposed between a battery and an electric load, and the relay circuit is sealed in a case of a battery pack. The relay circuit includes: a first main relay disposed in a first conduction path which is connected to a first terminal of the battery; a second main relay disposed in a second conduction path which is connected to a second terminal of the battery; and a pre-charge relay connected to the second conduction path in parallel with the second main relay. The relay control device turns on the pre-charge relay, the first main relay, and the second main relay in order, and then turns off the pre-charge relay, the first main relay, and the second main relay in order.

Abstract: A power switch circuit of adaptively limiting a current is provided. The power switch circuit includes a current sensing resistor, a power switch, a charge pump and an adaptive current limiting circuit. A first terminal of the current sensing resistor is coupled to an input voltage. A first terminal of the power switch is connected to a second terminal of the current sensing resistor. A second terminal of the power switch is connected to a first terminal of a capacitor. A second terminal of the capacitor is grounded. An output terminal of the charge pump is connected to a control terminal of the power switch. According to the input voltage, a voltage of the current sensing resistor and a voltage of the capacitor, the adaptive current limiting circuit determines whether to control an operation of the power switch for limiting the current flowing through the power switch.

Abstract: In an electromagnetic relay device, a mover includes a movable contact movable to abut onto and separate from a stationary contact through a contact region defined between the movable and the stationary contacts. A plunger causes the mover to reciprocate to accordingly cause the movable contact to abut onto or separate from the stationary contact. A solenoid unit of the electromagnetic relay device includes an electromagnetic coil, a movable core, and a support member that slidably supports an outer peripheral surface of a slidable contact portion of the movable core. A movable wall member is located between the slidable contact portion and the contact region. The movable wall member reciprocates together with the plunger. The movable wall member is arranged to occupy a region in the electromagnetic relay device. The region contains at least the slidable contact portion when viewed in the reciprocation direction.

Abstract: Characteristics of a semiconductor device having a non-volatile memory are improved. The non-volatile memory has the following configuration: a semiconductor substrate; a first gate electrode portion arranged over the semiconductor substrate; a second gate electrode portion arranged over the semiconductor substrate so as to be adjacent to the first gate electrode portion; a first insulating film formed between the first gate electrode portion and the semiconductor substrate; a second insulating film formed between the second gate electrode portion and the semiconductor substrate and having a charge storage portion therein; and a first side wall insulating film arranged on a side surface side of the second gate electrode portion opposite to the first gate electrode portion, the charge storage portion being made of a high dielectric constant film containing hafnium and oxygen, and a gap being provided between the first side wall insulating film and the charge storage portion.

Abstract: A semiconductor device includes a data path having a plurality of processor elements, a state transition management unit managing a state of the data path, and a parallel computing unit in which an input and an output of data is sequentially carried out, and an output of the parallel computing unit is capable of being handled by the plurality of processor elements.

Abstract: A semiconductor device includes a plurality of processors capable of executing a plurality of virtual machines and a cache memory. Each of the plurality of virtual machines executes a different operating system from each other. A hypervisor sets allocation information so as to allocate ways of the cache memory which can be used by the virtual machine. When outputting a memory access request, each of the processors outputs virtual machine identification in association with the information memory access request. When the memory access request is not a cache hit, the cache memory selects a way to be replaced data based on the virtual machine identification information and the allocation information.

Abstract: A semiconductor chip includes a first common marker generating circuit and a second common marker generating circuit. The first common marker generating circuit is configured to send a first request signal to the second common marker generating circuit, the first request signal requesting a common marker to be sent to a second trace memory, and to send the common marker to a first trace memory, when a second request signal is received from the second common marker generating circuit, the second request signal requesting the common marker to be sent to the first trace memory. The second common marker generating circuit is configured to send the common marker to the second trace memory and to send the second request signal to the first common marker generating circuit, if a second core is running a user program at a time when the first request signal is received.

Abstract: A performance of a semiconductor device including a main MOSFET and a sensing MOSFET having a double-gate structure including a gate electrode and a field plate electrode inside a trench is improved. A main MOSFET including a gate electrode and a field plate electrode inside a second trench and a sensing MOSFET for electric-current detection including a gate electrode and a field plate electrode inside a fourth trench are surrounded by different termination rings, respectively.

Abstract: A hub transmission direction control method, a hub and a control circuit are provided. The method includes processes of: detecting a clock signal of a host serial clock line; starting timing when the clock signal meets a trigger condition; when the timed time reaches a preset time, detecting a host data signal of a host data line communicated with a host device and a local data signal of a local data line communicated with a local device; and setting, according to a detection result of the host data signal and the local data signal, a first transmission direction in which data is transmitted from the host data line to the local data line, or a second transmission direction in which data is transmitted from the local data line to the host data line, as a transmission direction between the host data line and the local data line.

Abstract: An electrical test of a semiconductor device is conducted by electrically connecting a plurality of leads of the semiconductor device with a plurality of electrodes of a test board via a plurality of socket terminals of a socket of a test apparatus, respectively. At least a part of the socket is disposed inside a chamber of the test apparatus, and the test board is disposed outside the chamber. The semiconductor device is to be cooled by a cool air circulating in the chamber. The socket has a cavity portion through which the cool air circulating in the chamber can pass, and a part of each of the plurality of socket terminals is exposed in the cavity portion of the socket. The plurality of socket terminals is to be cooled by the cool air passing through the cavity portion of the socket.

Abstract: A semiconductor device according to one embodiment includes an IGBT having a p-type collector layer and an n-type field stop layer on a back surface of a silicon substrate. The n-type field stop layer is selectively provided on an upper side of the p-type collector layer such that a first end portion of the n-type field stop layer is separated from a first side surface of the silicon substrate by a predetermined distance, and an n-type drift layer is provided between the first side surface of the silicon substrate and the first end portion of the n-type field stop layer. An impurity concentration of the n-type drift layer is lower than an impurity concentration of the n-type field stop layer.