Abstract: A washer control device includes a computer configured to: monitor a motor current value that is a value of electric current supplied to a washer motor; acquire an energization time for which the electric current is supplied to the washer motor; and calculate a usage amount of a washer fluid from the motor current value and the energization time, and calculate, as a margin of the washer fluid, a remaining amount of the washer fluid in a washer tank based on the usage amount.

Abstract: A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.

Abstract: An insulating film is formed on a semiconductor substrate, and a silicon film is formed on the insulating film. The silicon film and the insulating film in a transistor forming region are removed, and the silicon film and the insulating film in a transistor forming region are left. An insulating film is formed on the semiconductor substrate in the transistor forming region. A Hf-containing film is formed on the insulating film and the silicon film, and a silicon film is formed on the Hf-containing film. Then, a gate electrode is formed by patterning the silicon film, and a gate electrode is formed by patterning the silicon film. A gate insulating film under the gate electrode is formed by the insulating film, and a gate insulating film under the gate electrode is formed by the insulating film and the Hf-containing film.

Abstract: A memory cell which is a non-volatile memory cell includes a gate insulating film having a charge storage layer capable of retaining charge and a memory gate electrode formed on the gate insulating film. The charge storage layer includes a first insulating film containing hafnium and silicon and a second insulating film formed on the first insulating film and containing hafnium and silicon. Here, a hafnium concentration of the first insulating film is lower than a hafnium concentration of the second insulating film, and a bandgap of the first insulating film is larger than a bandgap of the second insulating film.

Abstract: A lighting device suitable for freezers includes a housing and a light source arranged in the housing. The lighting device further includes a light-transmitting member arranged within the light-emitting range of the light source. The light-transmitting member includes a first light-transmitting portion for irradiating the upper portion of the freezer, a second light-transmitting portion for irradiating the middle of the freezer, and a third light-transmitting portion for irradiating the lower portion of the freezer. The light-emitting surfaces of the first light-transmitting portion and the second light-transmitting portion are planes and the light-emitting surface of the third light-transmitting portion is in form of a stepped surface. The lighting device of the present disclosure makes items in the freezer irradiated more evenly, significantly convenient for the users.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: The wiring board has a first region overlapping a first semiconductor device and a second region not overlapping each of the first semiconductor device and a second semiconductor device. A first signal wiring of the wiring board has a first portion in the first region and a second portion in the second region. In a thickness direction of the wiring board, the second portion is between two ground patterns to which a reference potential is supplied, while the first portion has a portion not positioned between two ground patterns to which a reference potential is supplied. The first portion has a first wide portion having a larger width than a width of the second portion.

Abstract: An electromagnetic relay device includes a mover, a plunger, and a solenoid unit that causes the plunger to reciprocate. The mover includes a movable contact movable to abut onto or separate from a stationary contact. The plunger causes the mover to reciprocate to accordingly cause the movable contact to abut onto or separate from the stationary contact. A heat-resistant member is interposed between the insulator and the mover. The plunger enables indirect abutment onto the mover through the insulator and the heat-resistant member. A heat-resistant temperature of the heat-resistant member is set to be higher than that of the insulator.

Abstract: A technique capable of normally transmitting a LPM token from a transceiver to a USB device is provided. A semiconductor device includes: a controller including a first interface circuit in conformity with UTMI+ standards; a converting circuit including a second interface circuit in conformity with the UTMI+ standards and a third interface circuit in conformity with ULPI standards, the second interface circuit converting data transmitted from the first interface circuit and received, and the third interface circuit transmitting the converted data; a first circuit analyzing a packet output from the controller and identifying and holding a packet identifier contained in the packet; and a second circuit providing a transmission command, after which a data string containing the packet identifier indicating LPM bringing a USB device to a low power consumption state is added, if the first circuit determines that the packet identifier is the LPM.

Abstract: The present invention provides an electronic component that can be colored without the need for a dedicated furnace and a manufacturing method for the electronic component. A casing is formed of a resin material. A cover is formed of the resin material including an oxide layer on a surface, is attached to the casing, and includes an opening. A rotor is arranged inside the casing, and includes an operating portion exposed through the opening of the cover. The cover has a color different from that of the rotor.

Abstract: An active period that is expressed by a range of a count value t[x] and is a period during which communication of a packet with an outside is permitted and an inactive period that is expressed by a range of the count value t[x] and is a period during which communication of a packet with an outside is prohibited are defined in schedule data. A wireless communication interface communicates a packet with the outside during the active period. A power supply controller cuts off power supplied to the wireless communication interface during the inactive period. A synchronous controller updates a count value of a counter based on a synchronous data value in the received packet during a reception operation of the packet, define the synchronous data value based on the updated count value t[y] during a transmission operation of the packet, and store it in the packet to be transmitted.

Abstract: A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.

Abstract: A visual inspection apparatus includes a stage on which a FCBGA type semiconductor package having a lid is placed, a camera located above the stage, a coaxial illumination device located between the camera and the stage, an oblique illumination device located between the camera and the stage, and a control device. The control device is configured to irradiate the FCBGA type semiconductor package with illumination lights by the coaxial illumination device and the oblique illumination device, capture the FCBGA type semiconductor package by the camera to obtain the captured image, integrate a number of pixels of a predetermined pixel value by a binarization process of the captured image to obtain a determination value, and compare the determination value with a predetermined value to determine a non-defective product or a defective product.

Abstract: A motor driver of setting pulse width modulation at commutation time points of a motor is provided. A commutation control circuit outputs a phase control signal and a commutation starting signal according to a preset phase angle and a commutation signal of the motor. A pulse width modulation calculating circuit determines a starting time point of each of a plurality of cycles of a pulse width modulation signal according to the commutation starting signal. The pulse width modulation calculating circuit determines time of each of the plurality of cycles of the pulse width modulation signal according to the phase control signal. The pulse width modulation calculating circuit determines widths of a plurality of pulse waves of the pulse width modulation signal according to a target rotational speed of the motor. A motor driver circuit drives the motor according to the pulse width modulation signal.

Abstract: The semiconductor device 10 receives an input signal given from the signal generating unit provided externally by a plurality of receiving units, a receiving unit 12, 13 for generating a plurality of received signals from the received input signal, a plurality of received signals by comparing, an error determination unit 14 for outputting an error notification to the upper system in response to the error between the channels that occurs between the received signals becomes equal to or greater than the threshold value, the threshold count value is stored and a threshold count register 17, the error determination unit 14 waits for the departure of the error notification until the period specified by the threshold count value has elapsed.

Abstract: In a semiconductor device, an arithmetic circuit of a chip on a first stage performs a predetermined arithmetic operation on an input N-bit (N=4) selection signal. Similarly, an arithmetic circuit of each of chips on second and subsequent stages among chips on a total of M stages (M>N?2, M=16) performs a predetermined common arithmetic operation on an operation result of the arithmetic circuit of the chip on the preceding stage. A determination circuit provided in each chip performs a predetermined common logic operation on a bit string of the N-bit signal, which is the operation result of the corresponding arithmetic circuit, thereby determining whether it is the chip selected by the selection signal.

Abstract: A Semiconductor device includes a semiconductor substrate, an insulating film, a first conductive film, a ferroelectric film, an insulating layer, a first plug and a second plug. The semiconductor substrate includes a source region and a drain region which are formed on a main surface thereof. The insulating film is formed on the semiconductor substrate such that the insulating film is located between the source region and the drain region in a plan view. The first conductive film is formed on the insulating film. The ferroelectric film is formed on the first conductive film. The insulating layer covers the first conductive film and the ferroelectric film. The first plug reaches the first conductive film. The second plug reaches the ferroelectric film. A material of the ferroelectric film includes hafnium and oxygen. In plan view, a size of the ferroelectric film is smaller than a size of the insulating film.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

Abstract: The designing method according to an embodiment of the present invention is a method of designing a transmission line portion coupled between a transmission unit and a receiving unit, and transmitting a signal from the transmission unit to the receiving unit. Also, one-data-width distance is obtained by converting one-data-width interval, which is corresponding to a sampling period of an equalizer provided in one of the transmission unit and the receiving unit, to a distance. Further, a first reflection source for reflecting the signal is arranged at a position of the transmission line portion, where is corresponding to a ½-data-width distance corresponding to a half of the one-data-width distance. Here, the position corresponds to a grid point where a row grid line drawn on a screen used in the designing method and a column grid line drawn on the screen intersect with each other.

Abstract: A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.