Patents Assigned to ELECTRONICS CORPORATION
  • Patent number: 12334410
    Abstract: A semiconductor device includes an aluminum layer, a passivation film, and a protective film arranged between the aluminum layer and the passivation film. A plurality of aluminum regions are formed in the aluminum layer. A width of a gap between the adjacent aluminum regions is equal to or less than twice a thickness of the protective film 140. The gap is filled with the protective film 140.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: June 17, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Aoki, Takehiro Ueda
  • Patent number: 12327439
    Abstract: A drive-through vehicle diagnostic system for use in a drive-through track of a facility includes an offer generating module capable of presenting an offer to a user adjacent the track and receiving user input associated with a selected offer. A remote server is in communication with the offer generating module and is capable of generating a diagnostic procedure associated with the selected offer. The diagnostic procedure includes a prescribed data retrieval instruction and a prescribed diagnostic summary instruction. A scan tool is connectable with a vehicle and is configured to receive the prescribed data retrieval instruction and retrieve diagnostic data from the vehicle in accordance with the prescribed data retrieval instruction while the vehicle proceeds along the track. The remote server is configured to receive the retrieved diagnostic data and analyze the diagnostic data to generate a diagnostic summary in accordance with the prescribed diagnostic summary instruction.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: June 10, 2025
    Assignee: INNOVA ELECTRONICS CORPORATION
    Inventors: Hoa Chau, Phuong Pham, Bruce Brunda
  • Patent number: 12327665
    Abstract: A resistor material including a plurality of crystalline phases having a positive temperature coefficient of resistance, and an amorphous phase having a negative temperature coefficient of resistance and having a resistivity higher than the crystalline phase, in a mixed state, is provided. Moreover, a resistor element having a resistor film configured by the resistor material described above, and a method of manufacturing a resistor element by forming a film of an amorphous material having a negative temperature coefficient of resistance and subjecting this film to an annealing treatment to obtain the resistor element described above, are provided.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: June 10, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Nozomi Ito, Yorinobu Kunimune, Kenichiro Abe, Nobuhito Shiraishi
  • Patent number: 12327606
    Abstract: A semiconductor device according to an embodiment includes a level detection unit that validates a level detection signal LD when a value indicated by stream data exceeds a threshold condition value, a ring buffer that cyclically stores internal data generated from the stream data in a storage area that is set within a predetermined address range, a data processing unit that operates with a bus clock and performs data processing using the internal data acquired from the ring buffer, and an address adjustment unit that adjusts a read address indicating a read start position of the ring buffer to a position that becomes a predetermined difference from a write address of the ring buffer at that time in accordance with a start of generation of the bus clock, and generates a bus clock during a period in which the level detection signal LD is valid.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: June 10, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Motoshige Ikeda
  • Patent number: 12327585
    Abstract: Provided is a technology capable of initializing data in memory cells at a relatively high speed while suppressing an area increase. Based on a fact that the reset signal is turned to a high level, a control circuit of a semiconductor device turns a first transistor to an OFF state, a plurality of word lines to a selection state, a precharge circuit to the OFF state, column switches for writing to an ON state, and column switches for reading to the OFF state, causes write circuits to turn first bit lines and second bit lines to a low level and a high level, respectively, and initializes a plurality of memory cells.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: June 10, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shunya Nagata, Kouji Satou
  • Patent number: 12322708
    Abstract: In a semiconductor device in a wafer state, an element region and a scribe region are defined in one main surface of a semiconductor substrate. In the element region, a vertical MOS transistor is formed as a semiconductor element. In the scribe region, an n-type column region and a p-type column region are defined. An n-type column resistor is formed in the n-type column region. A p-type column resistor is formed in the p-type column region.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: June 3, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takehirou Mariko, Yasuhiro Okamoto, Senichirou Nagase
  • Patent number: 12316218
    Abstract: A power converter having a charge pump frequency switching control mechanism is provided. In the power converter, frequencies of a plurality of pulse waves of a clock signal are determined, according to a level of a high-side control signal outputted to a control terminal of a high-side switch from a control circuit or a voltage of the control terminal (and a voltage of a second terminal) of the high-side switch. In the power converter, a charge pump supplies power to a high-side driver circuit at the frequencies of the clock signal, and the high-side driver circuit uses the power from the charge pump to drive the high-side switch and to pull up the voltage of the control terminal of the high-side switch.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: May 27, 2025
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Kun-Min Chen
  • Patent number: 12314145
    Abstract: A semiconductor device includes first and second processor cores configured to perform a lock step operation and including first and second scan chains. The semiconductor device further includes a scan test control unit that controls a scan test of the first and second processor cores using the first and second scan chains, and a start-up control unit that outputs a reset signal for bringing the first and second processor cores into a reset state. The start-up control unit outputs an initialization scan request before the start of a lock step operation, and the scan test control unit performs an initialization scan test operation on the first and second processor cores by using an initialization pattern.
    Type: Grant
    Filed: August 18, 2023
    Date of Patent: May 27, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kiyoshi Hayase, Yuki Hayakawa, Toshiyuki Kaya, Kyohei Yamaguchi, Takahiro Irita, Shinichi Shibahara
  • Patent number: 12302610
    Abstract: A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: May 13, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hitoshi Maeda, Yoshiyuki Kawashima
  • Patent number: 12297366
    Abstract: A quantum dot oil-based ink is provided. The quantum dot oil-based ink includes a quantum dot material, a dispersing solvent, a viscosity modifier, and a surface tension modifying solution. The dispersing solvent includes a linear alkane having 6 to 14 carbon atoms. The viscosity modifier includes an aromatic hydrocarbon having 10 to 18 carbon atoms or a linear olefin having 16 to 20 carbon atoms. The surface tension modifying solution includes a hydrophobic polymer material and a nonpolar solvent.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: May 13, 2025
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Chun Che Lin, Chong-Ci Hu, Yi-Ting Tsai, Ching-Yi Chen, Yu-Chun Lee
  • Patent number: 12293162
    Abstract: A semiconductor device includes: a local memory outputting a plurality of pieces of weight data in parallel; a plurality of product-sum operation units corresponding to the plurality of pieces of weight data; and a plurality of unit selectors corresponding to the product-sum operations units, supplied with a plurality of pieces of input data in parallel, selecting the one piece of input data from the supplied plurality of pieces of input data according to a plurality of pieces of additional information each indicating a position of the input data to be calculated with the corresponding product-sum arithmetic unit calculator in the pieces of input data, and outputting the selected input data. Each of the plurality of product-sum arithmetic units performs a product-sum operation between the weight data different from each other in the plurality of pieces of weight data and the input data outputted from the corresponding unit selector.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: May 6, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Taro Fujii, Katsumi Togawa, Teruhito Tanaka, Takao Toi
  • Patent number: 12293925
    Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: May 6, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Murayama, Makoto Koshimizu, Takahiro Mori, Junjiro Sakai, Satoshi Iida
  • Patent number: 12294292
    Abstract: A power converter having a feedback voltage adjusting mechanism for a negative voltage is provided. Input terminals of an operational amplifier are respectively connected to a zero voltage and a first terminal of a first resistor. A second terminal of the first resistor is connected to a second terminal of a low-side switch. A first current source is connected to an output terminal of the operational amplifier and a first terminal of a second resistor. A second terminal of the second resistor is connected to the first terminal of the first resistor. The first current source outputs a first current according to a signal output by the operational amplifier. A second current source outputs a second current being m times the first current and is connected to a first terminal of a third resistor. A voltage of the first terminal of the third resistor is a feedback voltage.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: May 6, 2025
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Ming-Liang Tsai
  • Patent number: 12289918
    Abstract: The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: April 29, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 12288806
    Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: April 29, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kodai Ozawa, Sho Nakanishi
  • Patent number: 12288760
    Abstract: A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: April 29, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takayuki Igarashi, Hirokazu Sayama
  • Patent number: 12288467
    Abstract: A collision avoidance system includes a periphery monitoring system which detects vehicles in proximity to a subject vehicle by use of a sensor, an approaching vehicle notifying system which communicates with another vehicle in proximity to the subject vehicle in vehicle-to-vehicle communication, and a detected vehicle comparison/determination system which is connected to the periphery monitoring system and the approaching vehicle notifying system, determines common vehicles detected by both the periphery monitoring system and the approaching vehicle notifying system, and controls the periphery monitoring system and the approaching vehicle notifying system.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: April 29, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Suguru Fujita
  • Patent number: 12283908
    Abstract: A motor driver having a temperature sensing mechanism is provided. A control circuit determines a time for outputting a controlling signal according to a pulse-width modulation signal received from an external pulse-width modulation circuit. A driving circuit outputs a driving signal according to the controlling signal. An output stage circuit operates according to the driving signal to output an output stage signal to a motor to drive the motor to rotate. In a temperature sensing mode, a thermal sensor circuit senses a temperature inside the motor driver to output a temperature sensing signal. An external system circuit determines whether or not the motor driver causes overheating to the motor when being adapted to the motor according to the temperature sensing signal, and evaluates whether or not the motor driver is applicable to the motor.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: April 22, 2025
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Kun-Min Chen, Huan-Chieh Chou
  • Patent number: 12282056
    Abstract: A disconnection detector circuit that can favorably inspect a connection state of a wire without increase in parasitic capacitance is provided. A semiconductor device includes, in one package, a first integrated circuit including a transformer including a primary coil and a secondary coil, and a second integrated circuit connected to a midpoint and one end of the secondary coil. The second integrated circuit includes a reference line and a detector circuit. The reference line connects the midpoint of the secondary coil and a reference potential. On basis of a potential at a predetermined reference point of the first power supply line, the detector circuit detects whether a connection state between the second integrated circuit and the secondary coil is normal or abnormal.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: April 22, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Noboru Inomata
  • Patent number: 12278198
    Abstract: A semiconductor device includes a semiconductor package having a differential signal terminal pair, and a wiring board. The wiring board includes a first and a second signal transmission line and a reference potential plane. The first and the second signal transmission line is formed in a first conductive layer and connected to the differential signal terminal pair. The reference potential plane includes a conductive pattern formed in a different conductive layer from the first conductive layer. The conductive pattern includes a first and a second region overlapped with the first and the second signal transmission line in plan view, respectively. The conductive pattern has a plurality of openings in the first and the second region. An area of a first conductive portion of the reference potential plane in the first region becomes equal to an area of a second conductive portion of the reference potential plane in the second region.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: April 15, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshikazu Tanaka, Tadashi Kameyama, Takafumi Betsui