Patents Assigned to Elite Semiconductor Memory Technology Inc.
  • Patent number: 11070178
    Abstract: A class D power amplifier with novel design is provided. The amplifier includes an input stage, a periodic signal generator, a comparator, a power output stage, and a boost circuit. The input stage is coupled to a first supply voltage. The periodic signal generator generates a periodic signal and a reference signal. The power output stage is coupled to a second supply voltage. The boost circuit compares an output of the input stage with the reference signal, and thereby adjusts a value of the second supply voltage. The value of the second supply voltage is larger than a value of the first supply voltage. The reference signal is proportional to an amplitude of the periodic signal, and the amplitude of the periodic signal is determined by the value of the second supply voltage.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: July 20, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Shao-Ming Sun
  • Patent number: 11063511
    Abstract: A power control circuit includes an alternating current (AC) power source, a rectifier and a valley-fill circuit. The AC power source is configured to receive an AC voltage. The rectifier is configured to convert the AC voltage into a rectified voltage. The valley-fill circuit includes: an inductor, having a first terminal coupled to the rectifier, and a second terminal; a first resistor, having a first terminal coupled to the second terminal of the inductor, and a second terminal; a diode, having a cathode coupled to the second terminal of the inductor, and an anode; and a first capacitor, having a first terminal coupled to the second terminal of the first resistor and the anode of the diode, and a second terminal coupled to ground.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: July 13, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Che-Wei Hsu, Wun-Long Yu
  • Patent number: 10985157
    Abstract: An electrostatic discharge (ESD) protection device for a semiconductor device that includes a gate, a source including a silicide portion having a plurality of source contacts, and a drain including a silicide portion having a plurality of drain contacts, wherein the source and drain are extended away from the gate along a device axis. The ESD device includes a resist protective oxide (RPO) portion located on the semiconductor device in between the plurality of drain contacts and in between the plurality of source contacts, respectively.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 20, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Chien-Shao Tang, Ting-Jui Lin, Hsiang-Ming Chou, Fang-Yu Chang
  • Patent number: 10958259
    Abstract: A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: March 23, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Szu-Chun Tsao, Yang-Jing Huang, Ya-Mien Hsu
  • Patent number: 10916293
    Abstract: A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 9, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Ya-Chun Lai, Po-Hsun Wu, Jen-Shou Hsu
  • Patent number: 10797597
    Abstract: The present application proposes a transient enhancing circuit for a constant-on-time converter. The constant-on-time converter includes an error amplifier and a comparator. The transient enhancing circuit includes a first sample-and-hold circuit and a zero-current detection circuit. The first sample-and-hold circuit has an input terminal and an output terminal. The input terminal of the first sample-and-hold circuit is coupled to an output terminal of the error amplifier, and the output terminal of the first sample-and-hold circuit is coupled to a first input terminal of the comparator. The zero-current detection circuit is coupled to the first sample-and-hold circuit and arranged for outputting a control signal when current flowing through a load of the constant-on-time converter is detected to be zero. The present application also proposes a constant-on-time converter using the transient enhancing circuit.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 6, 2020
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Yao-Ren Chang
  • Patent number: 10796730
    Abstract: A semiconductor memory device includes a memory bank of an open bit-line architecture and a word-line decoder. The memory bank is divided into a plurality of memory blocks in a bit-line direction, and each of the memory blocks includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells which are grouped into a plurality of memory sections including two edge memory sections and at least one non-edge memory section. The word-line decoder generates a plurality of word-line enabling signals based on a plurality of address signals and activates one of the word lines for each of the two edge memory sections of one of the memory blocks and one of the word lines for one of the at least one non-edge memory section of each of the other memory blocks concurrently in an active mode according to the word-line enabling signals.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 6, 2020
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Yi Heng Liu, Jian-Sing Liou
  • Patent number: 10771017
    Abstract: An amplifier circuit with novel design is provided. The amplifier circuit includes an input stage, a resistor, an output stage, an intermediate stage and a gm circuit. The input stage is coupled to a first supply voltage, and is arranged to receive an input voltage and a feedback current. The resistor is coupled between the input voltage and the input stage. The output stage is coupled to a second supply voltage, and is arranged to provide an output voltage for driving a load. The intermediate stage is coupled between the input stage and the output stage, and includes a level shifter. The gm circuit is coupled to the input stage, and is arranged to compare the input voltage with a common mode voltage, and thereby generates a compensate current for the input stage.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: September 8, 2020
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Shao-Ming Sun
  • Patent number: 10672495
    Abstract: An E-fuse burning circuit comprising: a burning directing circuit, configured to receive first input data comprising first input address and burning directing data, to generate a burning directing signal according to the burning directing data; a ring address latch, configured to latch the first input address responding to a first clock signal, and configured to output second input address responding to the first clock signal; and a control signal generating circuit, configured to generate at least one stop signal to determine whether the data in the ring address latch is shifted or not. The ring address latch applies a first number of the stages when the burning directing signal indicates a row of the E-fuse circuit is to be burned and applies a second number of the stages when the burning directing signal indicates a column of the E-fuse circuit is to be burned.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: June 2, 2020
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Tse-Hua Yao, Yi-Fan Chen
  • Patent number: 10629282
    Abstract: An E-fuse circuit comprising: a ring address latch, configured to receive a first input address arranged in serial i bits responding to a first clock signal, and to output a second input address arranged in serial j bits responding to a second clock signal; a control signal generating circuit, configured to receive the second input address, and to decode the second input address to generate first control signals with m bits and second control signals with n bits, wherein the first control signals and the second control signals are transmitted in parallel, and m, n are factors of j; and an E-fuse group, comprising j fuses. If any one of the first control signals has a first logic value and any one of the second control signals has the logic value, a corresponding fuse the E-fuse group is burned.
    Type: Grant
    Filed: June 16, 2019
    Date of Patent: April 21, 2020
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Tse-Hua Yao, Yi-Fan Chen
  • Patent number: 10587196
    Abstract: A constant on-time controller has a voltage divider, a current ripple extractor, a one-shot on-timer, a comparator and a flip flop. The voltage divider generates a feedback voltage according to a regulator output voltage. The current ripple extractor senses a current in an energy storage inductor of a buck regulator flowing through flowing through an output capacitor's ESR, and generates an extracted ripple current having no DC component accordingly. The one-shot on-timer outputs a constant-on time control signal according to a buck regulator input voltage and the regulator output voltage. The modulation circuit outputs a modulation signal according to a reference voltage signal, the feedback voltage and the extracted ripple current. The flip flop generates a control signal to the buck regulator according to the modulation signal and the constant-on time control signal. An off-time of the buck regulator is determined according to the modulation signal.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 10, 2020
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: I-Hsiu Ho
  • Patent number: 10580505
    Abstract: An erasing method used in a flash memory having memory blocks is illustrated, each of the memory blocks is divided into a plurality of memory sectors, and steps of the erasing method is illustrated as follows. An erasing and verifying process is performed sequentially on the memory blocks or the memory sectors of the memory block according to a memory sector enable signal. An over-erased correcting and verifying process is performed sequentially on the memory blocks or the memory sectors of the memory block according to the memory sector enable signal, wherein the memory sector enable signal is set to be asserted if an over-erased correction is performed on at least one of the memory blocks or at least one of the memory sectors of the memory block.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 3, 2020
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Chih-Hao Chen
  • Patent number: 10542345
    Abstract: A virtual bass generating circuit used in a speaker is used to filter out a high frequency part of an audio signal to generate a low passed audio signal, generates an even and odd audio signals respectively having even and odd harmonics of the low passed audio signal according to the low passed audio signal, subtracts an amplified low passed audio signal from an addition of an amplified even audio signal and an amplified odd audio signal to generate a first calculated audio signal, filters out a low frequency part and a high frequency part of the first calculated audio signal to generate a band passed audio signal, and adds the band passed audio signal and the audio signal to generate a second calculated audio signal with enhanced even and odd harmonics of the audio signal.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: January 21, 2020
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Hsin-Yuan Chiu, Tsung-Fu Lin
  • Patent number: 10462860
    Abstract: A controller for a switching regulator of a LED lighting system has a current monitor, a voltage divider, an integration circuit, and a comparator circuit. The current monitor is used to sense a LED current passing through a current sensing resistor of the switching regulator, and to generate a sensing current. The voltage divider is used to receive the sensing current to generate a first through third divided voltages, wherein the first divided voltage is larger than the second divided voltage, and the second divided voltage is larger than the third divided voltage. The integration circuit is used to compare the second divided voltage with a reference voltage, and to generate an integration voltage across a RC circuit thereof accordingly. The comparator circuit is used to compare the integration voltage with the first divided voltage and the third divided voltage, and to generate a driving signal.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 29, 2019
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Tung-Ming Yu
  • Patent number: 10424386
    Abstract: An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address that has the under-erased transistor memory cell.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: September 24, 2019
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Chih-Hao Chen
  • Patent number: 10404227
    Abstract: A quaternary/ternary modulation selecting circuit of an amplifier includes: a signal generating circuit, a detecting circuit, and a selecting circuit. The signal generating circuit is arranged to generate a ternary signal and a quaternary signal. The detecting circuit coupled to the signal generating circuit is arranged to generate a mode selecting signal according to at least the ternary signal. The selecting circuit coupled to the signal generating circuit and the detecting circuit is arranged to select and output one of the ternary signal and the quaternary signal to an output stage of the amplifier according to the mode selecting signal.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: September 3, 2019
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Szu-Chun Tsao, Deng-Yao Shih
  • Patent number: 10297607
    Abstract: A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 21, 2019
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Takao Akaogi, Yider Wu, Yi-Hsiu Chen
  • Patent number: 10281943
    Abstract: A low dropout voltage regulator incorporates an N-channel MOS pass transistor, a main error amplifier, a first buffer circuit, an auxiliary error amplifier, a second buffer circuit, and a decision circuit. The auxiliary error amplifier consumes less bias current. In one embodiment, the decision circuit compares the portion of the output voltage with a bias voltage to control the gate of the N-channel MOS pass transistor, wherein the value of the bias voltage is less than the value of the reference voltage.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: May 7, 2019
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: I-Hsiu Ho
  • Patent number: 10256722
    Abstract: An oscillator includes a reference current generating circuit, a modulator circuit, and an oscillating circuit. The reference current generating circuit generates a first reference current. The modulator circuit generates a modulation current according to the first reference current and a feedback voltage, wherein the modulation current is negatively correlated with the feedback voltage. The oscillating circuit receives at least the modulation current, and generates an oscillating signal with an oscillating frequency according to at least the modulation current, wherein the oscillating frequency is varied according to the modulation current. The oscillator may be employed by a direct current (DC)-to-DC voltage converter.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 9, 2019
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Yao-Wei Yang
  • Patent number: 10203715
    Abstract: A bandgap reference circuit incorporates first, second, and third current sources, first and second amplifiers, first and second bipolar transistors, a feedback device, a first resistor, and a second resistor. The first resistor is coupled between one input of the second amplifier and the base of the first bipolar transistor. The second resistor is coupled between the base of the first bipolar transistor and the base of the second bipolar transistor. The first and second amplifies and the first to third current sources constitute negative feedback loops which force the voltages at the inputs of the amplifiers to be substantially equal.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 12, 2019
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Jian-Sing Liou