Abstract: A semiconductor memory device includes a memory bank of an open bit-line architecture and a word-line decoder. The memory bank is divided into a plurality of memory blocks in a bit-line direction, and each of the memory blocks includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells which are grouped into a plurality of memory sections including two edge memory sections and at least one non-edge memory section. The word-line decoder generates a plurality of word-line enabling signals based on a plurality of address signals and activates one of the word lines for each of the two edge memory sections of one of the memory blocks and one of the word lines for one of the at least one non-edge memory section of each of the other memory blocks concurrently in an active mode according to the word-line enabling signals.

Abstract: An amplifier circuit with novel design is provided. The amplifier circuit includes an input stage, a resistor, an output stage, an intermediate stage and a gm circuit. The input stage is coupled to a first supply voltage, and is arranged to receive an input voltage and a feedback current. The resistor is coupled between the input voltage and the input stage. The output stage is coupled to a second supply voltage, and is arranged to provide an output voltage for driving a load. The intermediate stage is coupled between the input stage and the output stage, and includes a level shifter. The gm circuit is coupled to the input stage, and is arranged to compare the input voltage with a common mode voltage, and thereby generates a compensate current for the input stage.

Abstract: An E-fuse burning circuit comprising: a burning directing circuit, configured to receive first input data comprising first input address and burning directing data, to generate a burning directing signal according to the burning directing data; a ring address latch, configured to latch the first input address responding to a first clock signal, and configured to output second input address responding to the first clock signal; and a control signal generating circuit, configured to generate at least one stop signal to determine whether the data in the ring address latch is shifted or not. The ring address latch applies a first number of the stages when the burning directing signal indicates a row of the E-fuse circuit is to be burned and applies a second number of the stages when the burning directing signal indicates a column of the E-fuse circuit is to be burned.

Abstract: An E-fuse circuit comprising: a ring address latch, configured to receive a first input address arranged in serial i bits responding to a first clock signal, and to output a second input address arranged in serial j bits responding to a second clock signal; a control signal generating circuit, configured to receive the second input address, and to decode the second input address to generate first control signals with m bits and second control signals with n bits, wherein the first control signals and the second control signals are transmitted in parallel, and m, n are factors of j; and an E-fuse group, comprising j fuses. If any one of the first control signals has a first logic value and any one of the second control signals has the logic value, a corresponding fuse the E-fuse group is burned.

Abstract: A quaternary/ternary modulation selecting circuit of an amplifier includes: a signal generating circuit, a detecting circuit, and a selecting circuit. The signal generating circuit is arranged to generate a ternary signal and a quaternary signal. The detecting circuit coupled to the signal generating circuit is arranged to generate a mode selecting signal according to at least the ternary signal. The selecting circuit coupled to the signal generating circuit and the detecting circuit is arranged to select and output one of the ternary signal and the quaternary signal to an output stage of the amplifier according to the mode selecting signal.

Abstract: An oscillator includes a reference current generating circuit, a modulator circuit, and an oscillating circuit. The reference current generating circuit generates a first reference current. The modulator circuit generates a modulation current according to the first reference current and a feedback voltage, wherein the modulation current is negatively correlated with the feedback voltage. The oscillating circuit receives at least the modulation current, and generates an oscillating signal with an oscillating frequency according to at least the modulation current, wherein the oscillating frequency is varied according to the modulation current. The oscillator may be employed by a direct current (DC)-to-DC voltage converter.

Abstract: An apparatus with load dump protection incorporates first and second half-bridge circuits, first and second comparators, and first and second clamping circuits. The first comparator compares a supply voltage with a first set voltage and generates a first comparison signal while the supply voltage exceeds the first set voltage. The second comparator compares the supply voltage with a second set voltage and generates a second comparison signal while the supply voltage exceeds the second set voltage. The first clamping circuit divides the supply voltage and provides a divided voltage to the first half-bridge circuit in response to the second comparison signal. The second clamping circuit divides the supply voltage and provides a divided voltage to the second half-bridge circuit in response to the second comparison signal.

Abstract: A memory auto repairing circuit including: a decoding circuit, a latch enable circuit and a first latch circuit, wherein the decoding circuit is arranged to compare a first input address with a plurality of fail addresses to generate a control signal; the latch enable circuit is arranged to selectively generate a first enable signal at least according to the control signal; and the first latch circuit is arranged to receive the first input address, and store the first input address when the first enable signal is received by the first latch circuit; wherein when the control signal indicates that the first input address is identical to one of the plurality of fail addresses, the enable signal is prevented from being transmitted from the latch enable circuit to the first latch circuit.

Abstract: A bootstrap circuit applied to a first transistor of a direct-current (DC) to DC converter includes a second transistor, a bootstrapping capacitor and a clamping circuit, wherein the bootstrapping capacitor has a first terminal and a second terminal, and the first terminal is coupled to a source terminal of a transistor, and the source terminal of the second transistor is coupled to the first transistor; and the clamping circuit is coupled between a gate terminal of the second transistor and the second terminal of the bootstrapping capacitor, and is arranged to maintain a voltage drop between the second terminal of the bootstrapping capacitor and the gate terminal of the second transistor. A drain terminal of the second transistor is coupled to a first reference voltage, and a maximum of a voltage level of the gate terminal of the first transistor is greater than the first reference voltage.

Abstract: Embodiments of the invention relate to a reference voltage pre-processing circuit and method for a reference voltage buffer. The embodiments include a filter to control/reduce the noise and/or interference attached to a reference voltage to be provided to a reference voltage buffer by passing the reference voltage via two transistor in series. Furthermore, the embodiments include an auxiliary voltage circuit which interfaces the filter and the reference voltage buffer to avoid that the reference voltage buffer get an invalid reference voltage.

Abstract: A clock generating circuit includes: a generating circuit, a reference circuit and an adjusting circuit. The generating circuit generates a clock signal. The reference circuit is coupled to the generating circuit, and generates a reference signal to the generating circuit according to the clock signal, wherein a frequency of the clock signal is varied according to the reference signal when the reference signal is received by the generating circuit. The adjusting circuit generates an adjusting signal and a trigger signal to the generating circuit, wherein the generating circuit refers to the trigger signal to decide whether to adjust the clock signal frequency according to the adjusting signal.

Abstract: A method for determining a resistance calibration direction in ZQ calibration of a memory device includes: repeatedly comparing a reference voltage with an target voltage by a comparator to obtain an odd plurality of comparison outputs, each of the comparison outputs being one of a high-level state and a low-level state; determining a majority of the comparison outputs for their states by a ZQ calibration controller; and determining a resistance calibration direction according to the majority by the ZQ calibration controller so that the ZQ calibration controller generates a calibration code based on the resistance calibration direction and applies the calibration code to a resistance calibration unit to adjust the target voltage via the resistance calibration unit.

Abstract: A memory device includes an address generation circuit, an address processing circuit and a refresh control circuit. The address generation circuit generates a first intermediate address according to a row address. The first intermediate address includes a first wordline address and an identification code indicating whether a first wordline indicated by the first wordline address is a normal or redundant wordline. The address processing circuit refers to the first intermediate address to generate a second intermediate address indicating a second wordline adjacent to the first wordline. The second intermediate address includes a second wordline address and an identification code indicating whether the second wordline is a normal or redundant wordline. The refresh control circuit determines a disturbance count of the second wordline each time the first wordline is activated, and refers to the disturbance count to determine whether to output the second wordline address to refresh the second wordline.

Abstract: A variable gain amplifying circuit incorporates an operational amplifier, an input device, a feedback device, a transconductance circuit, and a dynamic biasing circuit. The operational amplifier has an output terminal providing an amplified difference output signal. The input device has a first terminal receiving a first input signal, and a second terminal coupled to a first input terminal of the operational amplifier. The feedback device is coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The dynamic biasing circuit generates a bias current according to a set value. The transconductance circuit converts the difference between the first input signal and a second input signal into an analog output current flowing through the feedback device. The analog output current of the transconductance circuit is varied according to the bias current.

Abstract: A semiconductor device including: an output stage, including a PMOS, an NMOS and an output terminal, wherein a source terminal of the PMOS is connected to a first supply voltage, a drain terminal of the PMOS is connected to a drain terminal of the NMOS and the output terminal, a source terminal of the NMOS is connected to a second supply voltage, and the output terminal outputs an output signal; and a protection circuit, including a first voltage clamping circuit, including a first transistor, a second transistor and a first switch, wherein the first transistor and the second transistor are for clamping a gate voltage of the PMOS of the output stage and are connected in series, the first switch is coupled to the first supply voltage and a node between the first transistor and the second transistor for selectively coupling the first supply voltage to the node.

Abstract: A quaternary/ternary modulation selecting circuit of an audio amplifier includes a quaternary signal generating circuit, for receiving complementary analog input signals to generate complementary quaternary signals; and a ternary signal generating circuit for generating a ternary signal according to the complementary quaternary signals, wherein the ternary signal includes a positive ternary wave and a negative ternary wave; wherein when a difference in amplitude between the complementary analog input signals is within a predetermined range of zero amplitude, a signal pattern of the positive ternary wave generated from the ternary signal generating circuit is identical to a signal pattern of the negative ternary wave generated from the ternary signal generating circuit.

Abstract: A quaternary/ternary modulation selecting method of an audio amplifier includes: generating a ternary signal and a quaternary signal; generating a plurality of pulses with limited duty cycles; and selecting one of the quaternary signal, the ternary signal and the plurality of pulses for an output stage of the audio amplifier.

Abstract: An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on a wafer during a wafer level burn-in testing. According to one embodiment of the present invention, the test system comprises a probe card and n chips. The probe card comprises m first signal contacts for receiving m test signals from the tester, n second signal contacts for providing n test results to the tester, and a contact array. The probe card is in contact with the chips on the wafer through a plurality of needles. In this manner, the test system can detect whether the continuity fault condition exists in the path between the tester and the chips on the wafer during the wafer level burn-in testing.

Abstract: A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable.

Abstract: A control circuit applied in an e-fuse system selectively operates in a feeding mode and a reading mode. When the control circuit operates in the feeding mode, the control circuit is arranged to store a program code for indicating whether to connect a fuse of the e-fuse system thereto; and when the control circuit operates in the reading mode, the control circuit is arranged to read a state of the fuse of the e-fuse system coupled to the control circuit.