Patents Assigned to eMemory Technology Inc.
  • Patent number: 11030346
    Abstract: An integrated circuit includes a core circuit and a function lock circuit. The core circuit includes at least one function block circuit. The function lock circuit is coupled to the core circuit. The function lock circuit includes a random number source, an entanglement circuit, and a memory. The random number source is configured to generate a random code. The entanglement circuit is coupled to the random number source and the core circuit and configured to generate an unlocking code according to the random code and a command signal. The memory is coupled to the entanglement circuit and configured to store the unlocking code. The at least one function block circuit of the core circuit is determined to be locked/unlocked according to a presence of the unlocking code.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: June 8, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Hsin-Chou Liu
  • Patent number: 11031779
    Abstract: A memory system includes a non-volatile memory block, a random bit block, and a sense amplifier. The non-volatile memory block includes a plurality of non-volatile memory cells for storing a plurality of bits of data. Each of the non-volatile memory cells includes a first storage transistor. The random bit block includes a plurality of random bit cells for providing a plurality of random bits. Each of the random bit cells includes a second storage transistor and a third storage transistor. The sense amplifier senses a first read current of a non-volatile memory cell during a read operation of the non-volatile memory cell and senses a second read current of a random bit cell during a read operation of the random bit cell. The first storage transistor, the second storage transistor, and the third storage transistor are storage transistors of the same type.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 8, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Wein-Town Sun
  • Patent number: 11025054
    Abstract: An electrostatic discharge protection device is provided. A voltage selection circuit selects a voltage having a higher voltage value among a reference voltage and a voltage on a conductive path and supply the selected voltage to a RC latch self-feedback circuit, so that the RC latch self-feedback circuit ties a voltage of an input end of a RC control circuit when the electrostatic discharge does not occur, and disconnect a switch that conducts an electrostatic current.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: June 1, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Yun-Jen Ting, Chih-Wei Lai, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
  • Patent number: 11017862
    Abstract: A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 25, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chih-Hsin Chen
  • Patent number: 11012082
    Abstract: A multiphase clock generator includes a current mirror, a voltage controller, a pseudo-resistor circuit and a first delaying circuit. The current mirror includes a receiving terminal, a first mirroring terminal and a second mirroring terminal. The voltage controller is connected with the receiving terminal of the current mirror. A feedback terminal of the voltage controller is connected with the first mirroring terminal of the current mirror. A first terminal of the pseudo-resistor circuit is connected with the first mirroring terminal of the current mirror. A second terminal of the pseudo-resistor circuit is connected with a ground terminal. The first delaying circuit is connected with the second terminal of the pseudo-resistor circuit. An input terminal of the first delaying circuit receives a first input clock signal. An output terminal of the first delaying circuit generates a first delayed clock signal.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 18, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Che-Wei Chang
  • Patent number: 11011533
    Abstract: A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 18, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 11004505
    Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate. A method for operating the non-volatile memory cell includes, during a program operation, performing an initial program searching operation to identify a first initial value of a threshold voltage of the floating gate transistor, coupling the floating gate of the floating gate transistor to a first program voltage to raise the threshold voltage of the floating gate transistor, performing a program searching operation to identify a first variation of the threshold voltage, generating a second program voltage according to the first variation of the threshold voltage, and coupling the floating gate of the floating gate transistor to the second program voltage to raise the threshold voltage of the floating gate transistor.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: May 11, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Yih-Lang Lin
  • Patent number: 10991430
    Abstract: A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 27, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Chun-Fu Lin
  • Patent number: 10985758
    Abstract: A random code generator includes a memory cell, two write buffers and two sensing circuits. The memory cell includes a first program path between a first source line and a first bit line, a second program path between the first source line and a second bit line, a first read path between a second source line and a third bit line, and a second read path between a third source line and a fourth bit line. The two write buffers are connected with the first bit line and the second bit line, respectively. The two sensing circuits are connected with the third bit line and the fourth bit line, respectively. The two sensing circuits generate a first output signal and the second output signal to the corresponding write buffers according to the read currents in the corresponding read paths.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: April 20, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wei-Ming Ku, Wein-Town Sun, Ying-Je Chen
  • Patent number: 10944258
    Abstract: An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 9, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Wei Lai, Yun-Jen Ting, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
  • Patent number: 10930746
    Abstract: A differential type non-volatile memory circuit comprising a differential sensing circuit, a differential data line pair, a memory cell array, and a differential bit line pair is provided. The differential sensing circuit has a differential input terminal pair and a differential output terminal pair. The differential data line pair is electrically connected to the differential input terminal pair of the differential sensing circuit. The memory cell array has at least one differential non-volatile memory cell configured to store data. The differential bit line pair is electrically connected between the memory cell array and the differential data line pair. When logic states of the differential output terminal pair start to be different in a read operation phase of the memory cell array, the differential sensing circuit and the differential data line pair are disconnected.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 23, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chen-Hao Po, Cheng-Te Yang
  • Publication number: 20210050039
    Abstract: A method provided herein is adapted to a sense amplifier having a first cross-coupled latch and a second cross-coupled latch, each of which includes a first pair of transistors and a pair of coupling capacitors coupled to respective gate terminals of the first pair of transistors. The method includes, during a first phase, charging the pair of coupling capacitors of a first pair of transistors at a first cross-coupled latch to achieve zeroing and providing a first set of input voltages to a second cross-coupled latch, and, during a second phase following the first phase, discharging the pair of coupling capacitors to cancel a mismatch between the first pair of transistors and comparing the first set of input voltages provided to the second cross-coupled latch to generate a first set of output voltages.
    Type: Application
    Filed: June 25, 2020
    Publication date: February 18, 2021
    Applicant: eMemory Technology Inc.
    Inventor: Wei-Ming KU
  • Patent number: 10924112
    Abstract: A bandgap reference circuit is applied to the wide range supply voltage. When a power supply voltage is changed, the change amount of the bandgap voltage generated by the bandgap reference circuit is very low. The bandgap reference circuit includes a mirroring circuit, an input circuit and an operation amplifier. The mirroring circuit generates a first current, a second current and a third current to a first node, a second node and an output voltage of the bandgap reference circuit. The input circuit is connected with the first node to receive the first current and connected with the second node to receive the second current. A positive input terminal of the operation amplifier is connected with the first node. A negative input terminal of the operation amplifier is connected with the second node. An output terminal of the operation amplifier is connected with the mirroring circuit.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: February 16, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chia-Fu Chang
  • Patent number: 10916302
    Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate. A method for operating the non-volatile memory cell includes, during a program operation, performing an initial program searching operation to identify a first initial value of a threshold voltage of the floating gate transistor, coupling the floating gate of the floating gate transistor to a first program voltage to raise the threshold voltage of the floating gate transistor, performing a program searching operation to identify a first variation of the threshold voltage, generating a second program voltage according to the first variation of the threshold voltage, and coupling the floating gate of the floating gate transistor to the second program voltage to raise the threshold voltage of the floating gate transistor.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: February 9, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Yih-Lang Lin
  • Patent number: 10915464
    Abstract: A security system includes a physical unclonable function circuit, a write-in protection circuit, a memory, and a readout decryption circuit. The physical unclonable function circuit provides a plurality of random bit strings. The write-in protection circuit receives a write-in address and original data, and includes an address scrambling unit. The address scrambling unit generates a scrambled address by scrambling a write-in address according to a random bit string provided by the physical unclonable function circuit. The memory stores the storage data corresponding to the original data according to the scrambled address. The readout decryption circuit reads out the storage data from the memory according to the write-in address to derive the original data.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 9, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Meng-Yi Wu, Po-Hao Huang
  • Patent number: 10910062
    Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: February 2, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Hung-Hsiang Wang, Cheng-Te Yang, Chih-Hsin Chen
  • Patent number: 10892903
    Abstract: A communication system includes a first communication system and a second communication terminal. The first communication terminal generates a first shared key, and the second communication terminal generates a second shared key. During an exchange operation, the first communication terminal stores the second shared key of the second communication terminal, and the second communication terminal stores the first shared key of the first communication terminal. During a challenge operation, the first communication terminal sends a challenge string to the second communication terminal, the second communication terminal generates a response string by performing reversible encryption operations to the challenge string with the first shared key and the second shared key, the second communication terminal sends the response string to the first communication terminal, and the first communication terminal verifies the response string.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: January 12, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Meng-Yi Wu
  • Patent number: 10892266
    Abstract: A nonvolatile memory structure includes a substrate, a select transistor, and a floating-gate transistor. The substrate includes an oxide defined (OD) region and an erase region. The select transistor is disposed on the OD region, and the floating-gate transistor is disposed on the OD region between the select transistor and the erase region, wherein the floating gate has an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction. The OD region further has an addition region protruding in a second direction and partially overlapped with the floating gate, in which the second direction is vertical to the first direction.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 12, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Wein-Town Sun
  • Patent number: 10879797
    Abstract: A voltage booster circuit includes a primary charge pump circuit, a secondary charge pump circuit and a transistor. The primary charge pump circuit is used to convert a supply voltage into a boosted voltage in response to a clock signal. The secondary charge pump circuit is used to convert the supply voltage into a regulated voltage in response to the clock signal. The transistor is coupled to the primary charge pump circuit and the secondary charge pump circuit, and has a control terminal receiving the regulated voltage, a first terminal receiving the boosted voltage and a second terminal outputting an output voltage.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: December 29, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Fu Chang, Sung-Ling Hsieh
  • Patent number: 10847236
    Abstract: A memory cell includes a first anti-fuse element, a first select transistor, a second anti-fuse element, a second select transistor, and a sensing control circuit. The first anti-fuse element is coupled to an anti-fuse control line, and the first select transistor transmits a voltage between a first bit line and the first anti-fuse element according to a voltage on the word line. The second anti-fuse element is coupled to the anti-fuse control line. The second select transistor transmits a voltage between a second bit line and the second anti-fuse element according to the voltage on the word line. The sensing control circuit provides a discharging path to a system voltage terminal from the first select transistor or the second select transistor according to states of the first anti-fuse element and the second anti-fuse element during a read operation.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 24, 2020
    Assignee: eMemory Technology Inc.
    Inventor: Dung Le Tan Hoang