Patents Assigned to eMemory Technology Inc.
  • Publication number: 20240095411
    Abstract: A fault-injection protection circuit includes a circuit under protection and a detection circuit. The detection circuit includes a detection cell having unequal pull-up capability and pull-down capability, and is arranged at a distance less than a laser spot diameter from the circuit under protection. The detection circuit is used to generate an alarm signal upon detecting a laser fault injection.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 21, 2024
    Applicant: eMemory Technology Inc.
    Inventor: Dung Le Tan Hoang
  • Patent number: 11929434
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: March 12, 2024
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Patent number: 11915749
    Abstract: A resistive memory device includes word lines, first memory cells, second memory cells, bit lines, source lines, and a driver. The driver provides a forming voltage to the first memory cells and the second memory cells through the bit lines and the source lines in a forming process. A first connection length along the bit lines and the source lines between the first memory cells and the driver is longer than a second connection length along the bit lines and the source lines between the second memory cells and the driver. The forming process is performed to the first memory cells before the forming process is performed to the second memory cells. A first value of the forming voltage provided to the first memory cells is less than a second value of the forming voltage provided to the second memory cells.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: February 27, 2024
    Assignee: eMemory Technology Inc.
    Inventor: I-Lang Lin
  • Patent number: 11881274
    Abstract: A program control circuit for an antifuse-type one time programming memory cell array is provided. When the program action is performed, the program control circuit monitors the program current from the memory cell in real time and increases the program voltage at proper time. When the program control circuit judges that the program current generated by the memory cell is sufficient, the program control circuit confirms that the program action is completed.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 23, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chia-Fu Chang, Po-Ping Wang, Jen-Yu Peng
  • Publication number: 20240021246
    Abstract: A selection circuit includes a main selection circuit and an auxiliary selection circuit. When a first voltage and a second voltage are different, the main selection circuit selects a higher one of the first voltage and the second voltage as an output voltage. When the first voltage and the second voltage are equal, the auxiliary selection circuit generates the output voltage according to the first voltage and the second voltage.
    Type: Application
    Filed: May 9, 2023
    Publication date: January 18, 2024
    Applicant: eMemory Technology Inc.
    Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: 11877456
    Abstract: A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: January 16, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Ying-Je Chen, Wein-Town Sun, Chun-Hsiao Li, Hsueh-Wei Chen
  • Patent number: 11837282
    Abstract: A charge pump apparatus includes a first charge pump system, a second charge pump system, a switch transistor, and a voltage regulation circuit. The first charge pump system converts a first supply voltage into a first boost voltage. The second charge pump system converts a second supply voltage into a second boost voltage. The switch transistor is coupled to the first charge pump system and the second charge pump system, and outputs an output voltage according to the second boost voltage. The switch transistor includes a control terminal receiving the second boost voltage, a first terminal receiving the first boost voltage, and a second terminal outputting the output voltage. The voltage regulation circuit successively adjusts a code of a voltage regulation signal according to the output voltage, in order to control the second charge pump system to successively adjust the second boost voltage according to the voltage regulation signal.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: December 5, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Fu Chang, Sung-Ling Hsieh
  • Patent number: 11818887
    Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: November 14, 2023
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Hsueh-Wei Chen, Woan-Yun Hsiao, Wei-Ren Chen, Wein-Town Sun
  • Patent number: 11783905
    Abstract: When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: October 10, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Chieh-Tse Lee, Ting-Yang Yen, Cheng-Da Huang, Chun-Hung Lin
  • Publication number: 20230315393
    Abstract: A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Applicant: eMemory Technology Inc.
    Inventor: Ching-Hsiang Hsu
  • Patent number: 11749372
    Abstract: A memory device includes a data memory array, a reference memory array and a detection circuit. The reference memory array includes (N/2+1) bit lines, (N/2) source lines and reference cells, N being a positive even integer. Each row of reference cells includes a (2n?1)th reference cell and a (2n)th reference cell. The (2n?1)th reference cell includes a first terminal coupled to an nth bit line, and a second terminal coupled to an nth source line, n being a positive integer less than N/2+1. The (2n)th reference cell includes a first terminal coupled to an (n+1)th bit line, and a second terminal coupled to the nth source line. The detection circuit compares a data current outputted from the data memory array and a reference current outputted from the reference memory array to determine a data state of a memory cell.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: September 5, 2023
    Assignee: eMemory Technology Inc.
    Inventor: Cheng-Te Yang
  • Patent number: 11751398
    Abstract: A memory structure including a substrate, a gate structure, a charge storage layer, and a first control gate is provided. The substrate has a fin portion. A portion of the gate structure is disposed on the fin portion. The gate structure and the fin portion are electrically insulated from each other. The charge storage layer is coupled the gate structure. The charge storage layer and the gate structure are electrically insulated from each other. The first control gate is coupled to the charge storage layer. The first control gate and the charge storage layer are electrically insulated from each other.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: September 5, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Woan-Yun Hsiao, Wein-Town Sun
  • Patent number: 11735266
    Abstract: An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: August 22, 2023
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Lun-Chun Chen, Jiun-Ren Chen, Ping-Lung Ho, Hsin-Ming Chen
  • Patent number: 11716842
    Abstract: A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 1, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Shiau-Pin Lin, Chih-Min Wang
  • Patent number: 11709656
    Abstract: A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: July 25, 2023
    Assignee: eMemory Technology Inc.
    Inventor: Ching-Hsiang Hsu
  • Patent number: 11690221
    Abstract: A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: June 27, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Chiang Ong, Tsung-Ta Hsieh, Chih-Yang Huang
  • Patent number: 11663455
    Abstract: A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 30, 2023
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Tsung-Mu Lai, Wei-Chen Chang, Hsueh-Wei Chen
  • Patent number: 11665895
    Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 30, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Wein-Town Sun, Chun-Hsiao Li
  • Patent number: 11616360
    Abstract: An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: March 28, 2023
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Wei Lai, Yun-Jen Ting, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
  • Patent number: 11610103
    Abstract: A one time programmable non-volatile memory cell includes a storage element. The storage element includes a glass substrate, a buffer layer, a polysilicon layer and a metal layer. The buffer layer is disposed on the glass substrate. The polysilicon layer is disposed on the buffer layer. A P-type doped region and an N-type doped region are formed in the polysilicon layer. The metal layer is contacted with the N-type doped region and the P-type doped region. The metal layer, the N-type doped region and the P-type doped region are collaboratively formed as a diode. When a program action is performed, the first diode is reverse-biased, and the diode is switched from a first storage state to a second storage state. When a read action is performed, the diode is reverse-biased and the diode generates a read current.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: March 21, 2023
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wein-Town Sun, Woan-Yun Hsiao