Abstract: A multiply accumulate circuit receives m one-bit neuron values from a first layer of a neural network system. The multiply accumulate circuit includes m non-volatile memory cells and m current sources. In addition, m current paths are defined by the m non-volatile memory cells and the m current sources collaboratively. A first current path is defined by a first non-volatile memory cell and a first current source. A first terminal of the first current source receives a first supply voltage. A second terminal of the first current source is connected with a first terminal of the first non-volatile memory cell. A second terminal of the first non-volatile memory cell is connected with an output terminal of the multiply accumulate circuit. A control terminal of the first current source receives a first one-bit neuron value.

Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Abstract: A voltage level shifter is provided. The voltage level shifter includes a main level shifter, a first bias level shifter and a second bias level shifter. The main level shifter includes a first N-type transistor and a second N-type transistor cross-coupled to each other, a third N-type transistor and a fourth N-type transistor controlled by a first bias voltage, a fifth N-type transistor and a sixth N-type transistor respectively controlled by a second bias voltage and a third bias voltage, and a first P-type transistor and a second P-type transistor configured to respectively receive an input signal and an inverted input signal which have opposite voltage values. The first bias level shifter generates the first bias voltage according to an enable signal. The second bias level shifter generates the second bias voltage and the third bias voltage according to the first bias voltage and the input signal.

Abstract: A one-time-programmable (OTP) memory device includes an active region and a gate electrode layer. The active region includes a channel region having a channel layer and source/drain regions disposed on opposite sides of the channel region in a Y-direction. The gate electrode layer extends in an X-direction and wraps around the channel layer. A first thickness of the gate electrode layer from a first edge of a first end of the gate electrode layer to the channel layer in the X-direction is equal to a second thickness of the gate electrode layer from a second edge of a second end of the gate electrode layer to the channel layer in the X-direction. After the first end is connected to a first voltage and the second end is connected to a second voltage different to the first voltage, the first thickness is different to the second thickness.

Abstract: A level shifter which includes an inverter, first/second/third/fourth N-type transistors, first/second P-type transistors and a buffer is provided. The inverter inverts an input voltage to generate an inverted input voltage based on a first reference voltage. The first N-type transistor has a gate receiving the input voltage. The second N-type transistor has a gate receiving the inverted input voltage. The third N-type transistor has a source coupled to a drain of the first N-type transistor. The fourth N-type transistor has a source coupled to a drain of the second N-type transistor. Gates of the first/second P-type transistors are coupled to the drains of the second/first N-type transistors, respectively, and sources of the first/second P-type transistors receive a second reference voltage. The level shifter generates an output voltage according to a shifted voltage on the drain terminal of the third N-type transistor or the drain terminal of the fourth N-type transistor.

Abstract: A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.

Abstract: A one-time-programmable (OTP) memory device includes a memory array including an N-type memory cell and a P-type memory cell. The N-type memory cell includes first channel layers and second channel layers. The P-type memory cell includes third channel layers and fourth channel layers. The N-type memory cell and the P-type memory cell further include a first word-line gate structure extending in the Y-direction and wrapping around the first channel layers and the third channel layers, and an anti-fuse gate structure extending in the Y-direction and wrapping around the second channel layers and the fourth channel layers. The OTP memory device further includes a wall structure extending in an X-direction and between the N-type memory cell and the P-type memory cell in the Y-direction. The first channel layers, the second channel layers, the third channel layers, and the fourth channel layers attach on the wall structure.

Abstract: A voltage detecting circuit for a non-volatile memory is provided. When a standby signal is not asserted, a power supply unit of the non-volatile memory provides an array voltage to a first node. The voltage detecting circuit includes an initial voltage generator, a capacitor, a latch and a combinational logic circuit. The initial voltage generator receives an inverted standby signal and an enable signal. An output terminal of the initial voltage generator is connected with a second node. The capacitor is coupled between the first node and the second node. An input terminal of the latch is connected with the second node. An output terminal of the latch is connected with a third node. An input terminal of the combinational logic circuit is connected with the third node. An output terminal of the combinational logic circuit generates the enable signal.

Abstract: A voltage level shifter includes an input transistor, a control circuit, a reset circuit, and a keeper circuit. The input transistor is configured to receive an input voltage and a first reference voltage. The control circuit is configured to generate a pulse voltage according to the input voltage and one of a node voltage, an output voltage, and an inversion input voltage. The reset circuit is configured to receive the first reference voltage and a second reference voltage and controlled by the pulse voltage. The reset circuit is coupled to the input transistor at a first node where the node voltage is generated. The keeper circuit is coupled to the first node and configured to generate the output voltage according to the node voltage, the first reference voltage, the second reference voltage, and the output voltage.

Abstract: A cell array structure includes a first resistive memory cell. The first resistive memory cell includes a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region is formed under a surface of the well region. The merged region is formed under the surface of the well region. The first gate structure is formed over the surface of the well region between the first doped region and the merged region. The first gate structure includes a first insulation layer and a first conductive layer. The second gate structure is formed over the merged region. The second gate structure includes a second insulation layer and a second conductive layer. The first metal layer is connected with the first doped region.

Abstract: A forming control method for a resistive random-access memory cell array is provided. While a forming action of the resistive random-access memory cell array is performed, a verification action is performed to judge whether the forming action on the resistive random-access memory cells has been successfully done. By properly changing a forming voltage or a pulse width, the forming actions on all of the resistive random-access memory cells of the resistive random-access memory cell array can be successfully done.

Abstract: A sensing device for a non-volatile memory includes a reference circuit, two switches, a sensing circuit and a judging circuit. The reference circuit is connected to a first node. A first terminal of the first switch is connected with the first node and a control terminal of the first switch receives an inverted reset pulse. A first terminal of the second switch is connected with the first node, a second terminal of the second switch receives a ground voltage, and a control terminal of the second switch receives a reset pulse. The sensing circuit is connected between the second terminal of the first switch and a second node. The sensing circuit generates a first sensed current. The judging circuit is connected to the second node. The judging circuit receives the first sensed current and generates an output data according to the first sensed current.

Abstract: A driving circuit includes a cross coupled circuit, a first conducting device, a second conducting device, a first switching device, a second switching device, a first selecting device and a second selecting device. The first conducting device is connected between a first node and a second node. The second conducting device is connected between a third node and a fourth node. The cross coupled circuit receives a first supply voltage and is connected with the first node and the second node. The first switching device is connected between the second node and a fifth node. The second switching device is connected between the fourth node and a sixth node. The first and second selecting devices are respectively connected with the fifth node and the sixth node. Each of the first and second selecting devices receives a second supply voltage and a third supply voltage.

Abstract: A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.

Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.

Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.

Abstract: A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second floating gate transistor and a second select transistor. The first select transistor is connected with a program source line and a program word line. The first floating gate transistor includes a floating gate. The first floating gate transistor is connected with the first select transistor and a program bit line. The second floating gate transistor includes a floating gate. The second floating gate transistor is connected with a read source line. The second select transistor is connected with the second floating gate transistor, the read word line and the read bit line. The floating gate of the second floating gate transistor is connected with the floating gate of the first floating gate transistor.

Abstract: A fault-injection protection circuit includes a circuit under protection and a detection circuit. The detection circuit includes a detection cell having unequal pull-up capability and pull-down capability, and is arranged at a distance less than a laser spot diameter from the circuit under protection. The detection circuit is used to generate an alarm signal upon detecting a laser fault injection.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.