Patents Assigned to Engineering Technologies, Inc.
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Patent number: 7534632Abstract: A method for circuit inspection comprises steps of providing a substrate having a conductive line; and forming a metal layer on at least the conductive layer to increase a contrast between the conductive layer and adjacent area for the circuit inspection. The method further comprising removing the metal layer. The metal layer is removed by a mixture of nitric acid, hydrogen peroxide and fluoride boric acid. The metal includes Silver, Nickel or Tin. The deposit metal can be removed by inter diffusion and form intermetallic compounds (for example Cu6Sn5) into the under laying conducting line.Type: GrantFiled: February 20, 2007Date of Patent: May 19, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Yu-Shan Hu, Dyi-Chung Hu
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Publication number: 20090111743Abstract: The present invention provides a heparin binding growth factor analog of any of formula I-VIII and methods and uses thereof.Type: ApplicationFiled: February 23, 2006Publication date: April 30, 2009Applicant: BioSurface Engineering Technologies, Inc.Inventor: Kazuyuki Takahashi
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Patent number: 7525139Abstract: An image sensor die comprises a substrate and an image sensor array formed over the substrate. Micro lens are disposed on the image sensor array. A protection layer is formed on the micro lens to prevent the micro lens from particle containment.Type: GrantFiled: December 29, 2004Date of Patent: April 28, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Chin-Chen Yang, Wen-Ping Yang, Wen-Bin Sun, Chao-nan Chou, His-Ying Yuan, Jui-Hsien Chang
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Patent number: 7525185Abstract: The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate.Type: GrantFiled: March 19, 2007Date of Patent: April 28, 2009Assignee: Advanced Chip Engineering Technology, Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin, Tung-Chuan Wang, Hsien-Wen Hsu, Chih-Ming Chen
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Patent number: 7514767Abstract: To pick and place standard dice on a new base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type wafer level package. Moreover, the die may be packaged with passive components or other dice with a side by side structure or a stacking structure.Type: GrantFiled: July 7, 2006Date of Patent: April 7, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventor: Wen-Kun Yang
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Patent number: 7501310Abstract: An image sensor die comprises a substrate and an image sensor array formed over the substrate. Micro lens are disposed on the image sensor array. A protection layer is formed on the micro lens to prevent the micro lens from particle containment.Type: GrantFiled: November 27, 2007Date of Patent: March 10, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen-Pin Yang
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Patent number: 7498556Abstract: The present invention provides an image sensor module having build-in package cavity and the Method of the same. An image sensor module structure comprising a substrate with a package receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate, and a package having a die with a micro lens disposed within the package receiving cavity. A dielectric layer is formed on the package and the substrate, a re-distribution conductive layer (RDL) is formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces and the dielectric layer has an opening to expose the micro lens. A lens holder is attached on the substrate and the lens holder has a lens attached an upper portion of the lens holder. A filter is attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder.Type: GrantFiled: March 15, 2007Date of Patent: March 3, 2009Assignee: Adavanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin, Jui-Hsien Chang, Tung-Chuan Wang
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Patent number: 7498646Abstract: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises a metal alloy base, a wafer level package, a lens holder, and flexible printed circuits (F.P.C.). The wafer level package having a plurality of image sensor dice and a plurality of solder balls is attached to the metal alloy base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dice. The lens holder is placed in the flexible printed circuits (F.P.C.), and the flexible printed circuits (F.P.C.) has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dice. Moreover, the image sensor dice may be packaged with passive components or other dice with a side by side structure or a stacking structure.Type: GrantFiled: July 19, 2006Date of Patent: March 3, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen Kun Yang, Wen Pin Yang
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Patent number: 7482427Abstract: Compounds of the present invention of formula I and formula II are disclosed in the specification and wherein the compounds are modulators of Bone Morphogenic Protein activity. Compounds are synthetic peptides having a non-growth factor heparin binding region, a linker, and sequences that bind specifically to a receptor for Bone Morphogenic Protein. Uses of compounds of the present invention in the treatment of bone lesions, degenerative joint disease and to enhance bone formation are disclosed.Type: GrantFiled: February 22, 2005Date of Patent: January 27, 2009Assignees: BioSurface Engineering Technologies, Inc., Brookhaven Science AssociatesInventors: Paul O. Zamora, Louis A. Pena, Xinhua Lin, Kazuyuki Takahashi
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Patent number: 7476565Abstract: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.Type: GrantFiled: May 3, 2007Date of Patent: January 13, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen-Bin Sun, Hsi-Ying Yuan, Chun Hui Yu
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Patent number: 7468210Abstract: A thromboresistant coating for a medical device, method of coating and coated medical device, the coating including an in situ cross-linked co-polymer of a cross-linkable biomolecule, preferably an adsorbable biomolecule such as a heparin activity biomolecule with at least one prosthetic hydrophobic unit, and a multifunctional crosslinking agent, such as a bis-variant of polyethylene glycol, polyethylene oxide, or polyethylene glycol, wherein the crosslinking is by means of covalent complexation through at least two functional groups of the multifunctional crosslinking agent.Type: GrantFiled: December 10, 2003Date of Patent: December 23, 2008Assignee: BioSurface Engineering Technologies, Inc.Inventor: Paul O. Zamora
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Patent number: 7468544Abstract: A wafer level package comprises a wafer having a plurality of dice formed thereon; a thinner metal cover with a cavity formed therein attached on the wafer by an adhesive material to improve thermal conductivity of the package. A protection film is formed on back side of the metal cover and filled into the cavity, thereby facilitating for laser marking and obtaining a better sawing quality of the package.Type: GrantFiled: December 7, 2006Date of Patent: December 23, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventor: Wen-Kun Yang
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Patent number: 7459729Abstract: The present invention discloses a structure of package including: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.Type: GrantFiled: December 29, 2006Date of Patent: December 2, 2008Assignee: Advanced Chip Engineering Technology, Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-chuan Wang
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Patent number: 7453148Abstract: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.Type: GrantFiled: December 20, 2006Date of Patent: November 18, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Chun-Hui Yu, Chao-Nan Chou, Chih-Wei Lin, Ching-Shun Huang
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Publication number: 20080274579Abstract: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination. A transparent cover with coated IR filter is optionally formed over the micron lens area for protection.Type: ApplicationFiled: July 9, 2008Publication date: November 6, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-Chuan Wang
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Publication number: 20080274593Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.Type: ApplicationFiled: July 9, 2008Publication date: November 6, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin
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Patent number: 7446546Abstract: The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer also can get the testing outcome which is more accurate. Furthermore, the present invention helps the manufacturer to achieve a significant improvement in IC packaging process.Type: GrantFiled: March 14, 2007Date of Patent: November 4, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Cheng Chieh Tai
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Publication number: 20080251908Abstract: The present invention provides a semiconductor device package with the die receiving through hole and connecting through hole structure comprising a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad. A die is disposed within the die receiving through hole. An adhesion material is formed under the die and filled in the gap between the die and sidewall of the die receiving though hole. Further, a wire bonding is formed to couple to the bonding pads and the first contact pad. A dielectric layer is formed on the wire bonding, the die and the substrate. A second contact pad is formed at the lower surface of the substrate and under the connecting through hole structure.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin
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Publication number: 20080227696Abstract: A heparin-binding growth factor (HBGF) analog having two substantially similar sequences (homodimeric sequences) branched from a single amino acid residue, where the sequences are analogs of a particular HBGF that binds to a heparin-binding growth factor receptor (HBGFR), or alternatively that bind to a HBGFR without being an analog of any particular HBGF. The homodimeric sequences may be derived from any portion of a HBGF. The synthetic HBGF analog may be an analog of a hormone, a cytokine, a lymphokine, a chemokine or an interleukin, and may bind to any HBGFR. Further provided are preparations for medical devices, pharmaceutical compositions and methods of using the same.Type: ApplicationFiled: February 21, 2006Publication date: September 18, 2008Applicant: BioSurface Engineering Technologies, Inc.Inventors: Kazuyuki Takahashi, Paul O. Zamora
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Patent number: 7423335Abstract: An image sensor multi-chips package structure, includes a first package including a first chip with image sensors having first bonding pads and micro lens on a first active surface, a first die receiving window and first conductive inter-connecting through holes penetrated from a first upper contact pads on a first upper surface of the first chip to a first lower contact pads on a first lower surface of the first chip, wherein a first upper build up layer on the active surface of the first chip coupling from the first bonding pads to the first upper contact pads; a second package comprising a second chip having second bonding pads on a second active surface, a second die receiving window and second conductive inter-connecting through holes penetrated from a second upper contact pads of a second upper surface of the second chip to a second lower contact pads on a second lower surface of the second chip, wherein a second upper build up layers on the second upper surface for coupling from the second bonding padsType: GrantFiled: December 11, 2007Date of Patent: September 9, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang