Patents Assigned to Engineering Technologies, Inc.
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Patent number: 7416920Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.Type: GrantFiled: October 3, 2006Date of Patent: August 26, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Kuang-Chi Chao, Cheng-hsien Chiu, Chihwei Lin, Jui-Hsien Chang
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Publication number: 20080197435Abstract: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination. A transparent cover with coated IR filter is optionally formed over the micron lens area for protection.Type: ApplicationFiled: February 21, 2007Publication date: August 21, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-Chuan Wang
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Publication number: 20080197480Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with a die receiving through hole, a conductive connecting through holes structure and coupled the first contact pads on an upper surface and second contact pads on a lower surface of the substrate through a conductive connecting through holes. A first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though holes of the substrate. Then, a first conductive wire is formed to couple the first bonding pads and the first contact pads. Further, a second die having second bonding pads is attached on the first die. A second conductive wire is formed to couple the second bonding pads and the first contact pads. A plurality of dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.Type: ApplicationFiled: October 31, 2007Publication date: August 21, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin
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Publication number: 20080197474Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin
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Publication number: 20080197469Abstract: The present invention provides a structure of multi-chips package and Method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a gap between the die and the substrate to absorb thermal mechanical stress; therefore the thickness of the package is reduced and the CTE mismatch of the structure is reduced. The present invention also provides a structure for SIP with higher reliability and lower manufacturing cost. the process is simpler and it is easy to form the multi-chips package than the traditional one. Therefore, the present invention discloses a fan-out WLP with reduced thickness and good CTE matching performance.Type: ApplicationFiled: February 21, 2007Publication date: August 21, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Hsien-Wen Hsu, Ya-Tzu Wu, Ching-Shun Huang
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Patent number: 7414028Abstract: The invention provides synthetic heparin-binding growth factor analogs of formulas I or II as given in the specification, having two peptide chains branched from a dipeptide branch moiety composed of at least one and preferably two trifunctional amino acid residues, which peptide chain or chains bind a heparin-binding growth factor receptor. The synthetic heparin-binding growth factor analogs are useful as pharmaceutical agents, soluble biologics or as surface coatings for medical devices.Type: GrantFiled: February 4, 2005Date of Patent: August 19, 2008Assignee: BioSurFace Engineering Technologies, Inc.Inventors: Paul O. Zamora, Louis A. Pena, Xinhua Lin
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Publication number: 20080191333Abstract: The present invention provides a structure of package comprising a substrate with a die through hole and a contact through holes structure formed there through, wherein a terminal pad is formed under the contact through hole structure and a contact pad is formed on a upper surface of the substrate. A die having a micro lens area is disposed within the die through hole by adhesion. A wire bonding is formed on the die and the substrate, wherein the wire bonding is coupled to the die and the contact pad. A protective layer is formed to cover the wire bonding. A transparent cover is disposed on the die within the die through hole by adhesion to expose the micro lens area. Conductive bumps are coupled to the terminal pads.Type: ApplicationFiled: February 8, 2007Publication date: August 14, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin, Jui-Hsien Chang, Tung-chuan Wang, Hsien-Wen Hsu
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Publication number: 20080173792Abstract: The present invention provides an image sensor module structure comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate and a die having a micro lens disposed within the die receiving cavity. A dielectric layer is formed on the die and the substrate, a re-distribution conductive layer (RDL) is formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces and the dielectric layer has an opening to expose the micro lens. A lens holder is attached on the substrate and the lens holder has a lens attached an upper portion of the lens holder. A filter is attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder.Type: ApplicationFiled: January 23, 2007Publication date: July 24, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-chuan Wang, Chihwei Lin, Hsien-Wen Hsu
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Publication number: 20080157398Abstract: The present invention provides a semiconductor device package having pseudo chips structure comprising a first substrate with die receiving through holes formed thereon; a first die having first bonding pads and a second die having second bonding pads disposed within the die receiving through holes, respectively; an adhesion material formed in the gap between the first and second die and sidewalls of the die receiving though holes of the first substrate; redistribution lines formed to couple the first contact pads formed on the first substrate to the first bonding pads and the second bonding pads, respectively; and a protection layer formed on the redistribution lines, the first die, the second die and the first substrate.Type: ApplicationFiled: June 26, 2007Publication date: July 3, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Chi-Chen Lee, Wen-Ping Yang
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Patent number: 7342296Abstract: The present invention provides a separating process of a semiconductor device package of wafer level package. The method comprises a step of etching a substrate to form recesses. Then a buffer layer is formed on the first surface of the substrate, wherein the buffer layer is filled with the corresponding recesses to form infillings on adjacent the semiconductor device package. Dicing the wafer into individual package along substantial center of said infillings, the step may avoid the roughness on the edge of each die and also decrease the cost of the separating process.Type: GrantFiled: December 5, 2005Date of Patent: March 11, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang
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Patent number: 7339279Abstract: The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.Type: GrantFiled: May 11, 2007Date of Patent: March 4, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventor: Wen Kun Yang
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Patent number: 7335870Abstract: The method of forming image sensor protection comprises attaching a glass on a tape and scribing the glass with lines to define cover zones on the glass, the glass is then break by a rubber puncher followed by forming glue on the edge of the cover zones. The glass is bonded on a wafer with an image sensor to align the cover zones to a micron lens area of the image sensor, and then the tape is removed from the wafer, thereby forming glass with cover zones on the image sensor.Type: GrantFiled: October 6, 2006Date of Patent: February 26, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Hsien-Wen Hsu
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Patent number: 7331248Abstract: A method and an apparatus for detecting, locating, and quantifying explosive materials and devices, and naturally occurring and man-made dangerous or hazardous biological and chemical materials and devices in ducts or piping systems, or other fluid flow systems in buildings such as residential, office, industrial, and power plants, transportation systems such as ships, airplanes, subways, and trains, and various types of infrastructure such as dams, tunnels, or bridges, and in the rooms, compartments, enclosures, containers, or difficult to access areas in these buildings, transportation systems, and structures. The preferred embodiment of this detection and location method uses a conservative tracer and one or more interactive tracers that are injected into the duct or area to be searched at one location and then monitored at the same or another location in the duct or area.Type: GrantFiled: October 6, 2004Date of Patent: February 19, 2008Assignee: Vista Engineering Technologies, Inc.Inventors: Joseph W. Maresca, Jr., Wesley L. Bratton
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Publication number: 20080017941Abstract: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises a metal alloy base, a wafer level package, a lens holder, and flexible printed circuits (F.P.C.). The wafer level package having a plurality of image sensor dice and a plurality of solder balls is attached to the metal alloy base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dice. The lens holder is placed in the flexible printed circuits (F.P.C.), and the flexible printed circuits (F.P.C.) has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dice. Moreover, the image sensor dice may be packaged with passive components or other dice with a side by side structure or a stacking structure.Type: ApplicationFiled: July 19, 2006Publication date: January 24, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen Kun Yang, Wen Pin Yang
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Publication number: 20080020511Abstract: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises a metal alloy base, a wafer level package, a lens holder, and flexible printed circuits (F.P.C.). The wafer level package having a plurality of image sensor dice and a plurality of solder balls is attached to the metal alloy base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dice. The lens holder is placed in the flexible printed circuits (F.P.C.), and the flexible printed circuits (F.P.C.) has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dice. Moreover, the image sensor dice may be packaged with passive components or other dice with a side by side structure or a stacking structure.Type: ApplicationFiled: April 27, 2007Publication date: January 24, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen Pin Yang
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Patent number: 7319043Abstract: The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer also can get the testing outcome which is more accurate. Furthermore, the present invention helps the manufacturer achieve a significant improvement in an IC packaging process.Type: GrantFiled: September 26, 2005Date of Patent: January 15, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Cheng Chieh Tai
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Publication number: 20070296065Abstract: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate to enhance reliability of the packaging structure.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Applicant: Advanced Chip Engineering Technology Inc.Inventors: Ming-Chih Yew, Chang-Ann Yuan, Chan-Yen Chou, Kou-Ning Chiang
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Patent number: 7297343Abstract: A wound dressing, method of making, and method of use, utilizing a polymeric film having complexed thereto by hydrophobic interaction a construct including a polyanion covalently bonded to a hydrophobic prosthetic moiety, with one or more bioactive molecules directly complexed to the polyanion. The polyanion may be heparin or a heparin-activity molecule. The prosthetic group may include a hydrophobic silyl-containing moiety. Bioactive molecules include adhesive molecules, growth factor molecules, and therapeutic molecules, including antibiotics.Type: GrantFiled: October 10, 2003Date of Patent: November 20, 2007Assignee: BioSurface Engineering Technologies, Inc.Inventor: Paul O. Zamora
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Patent number: 7279782Abstract: A structure of package comprises a die placed on printed circuit board. A glass substrate is adhered on an adhesive film pattern to form an air gap area between the glass substrate and the chip. Micro lens are disposed on the chip. A lens holder is fixed on printed circuit board. The glass substrate can prevent the micro lens from particle contamination.Type: GrantFiled: January 5, 2005Date of Patent: October 9, 2007Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Chin-Chen Yang, Wen-Bin Sun, Jui-Hsien Chang, Chun Hui Yu, His-Ying Yuan
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Patent number: 7259468Abstract: The present invention discloses a structure of wafer level packaging. The structure comprises a first patterned isolation layer, a conductive layer and a second patterned isolation layer. The first patterned isolation layer is formed with a passivation layer of an IC (Integrated Circuit). The conductive layer is configured to have a curved or winding conductive pattern. The second patterned isolation layer is formed over the conductive layer to have a plurality of openings, and contact metal balls can be formed on the openings to electrically couple to a print circuit board.Type: GrantFiled: April 30, 2004Date of Patent: August 21, 2007Assignee: Advanced Chip Engineering Technology Inc.Inventor: Wen-Kun Yang