Patents Assigned to Eudyna Devices Inc.
  • Patent number: 7745240
    Abstract: A manufacturing method of a light-emitting element includes emitting a laser light to a division region for separating a light-emitting element formed on a substrate, physically dividing the substrate along the division region, and removing a surface layer on at least one of the side faces of the substrate that is exposed by the dividing of the substrate.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: June 29, 2010
    Assignee: Eudyna Devices Inc.
    Inventor: Akira Furuya
  • Publication number: 20100151620
    Abstract: A semiconductor photo detecting element includes a PIN-type photo detecting element and window semiconductor layer. The PIN-type photo detecting element has a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer is provided on the semiconductor substrate, is lattice-matched to the semiconductor substrate, includes a first conductivity type dopant, and has first band gap energy. The second semiconductor layer is provided on the first semiconductor layer, has the first band gap energy, and has a concentration of the first conductivity type dopant lower than that of the first semiconductor layer or is substantially undoped. The third semiconductor layer is provided on the second semiconductor layer. The window semiconductor layer has second band gap energy larger than the first band gap energy at a light-incoming side with respect to the second semiconductor layer and has a thickness of 5 nm to 50 nm.
    Type: Application
    Filed: February 24, 2010
    Publication date: June 17, 2010
    Applicant: EUDYNA DEVICES INC.
    Inventors: Yoshihiro Yoneda, Ryuji Yamabi
  • Patent number: 7738844
    Abstract: A radio communication device includes: a local oscillator; an amplifier amplifying an output signal of the local oscillator and outputting a local oscillation frequency and a harmonic wave component thereof; and a harmonic mixer receiving an output signal of the amplifier and an information signal, and generating an up-converted signal of the information signal with the harmonic wave component based on the local oscillation frequency, while allowing the harmonic wave component to pass through.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: June 15, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Hiroshi Nakano, Yasutake Hirachi
  • Patent number: 7728353
    Abstract: A semiconductor device includes a mask layer having openings on a substrate, a GaN-based semiconductor layer selectively formed on the substrate with the mask layer that serves as a mask, a gate electrode and either a source electrode or an emitter electrode formed on the GaN-based semiconductor layer, and a drain electrode or a collector electrode connected on a surface of the first semiconductor layer that faces the GaN-based semiconductor layer or an opposite side of the first semiconductor layer.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: June 1, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Seiji Yaegashi, Takeshi Kawasaki, Ken Nakata
  • Patent number: 7723751
    Abstract: A semiconductor device includes a substrate, a SiC drift layer formed above the substrate, a GaN-based semiconductor layer that is formed on the SiC drift layer and includes a channel layer, a source electrode and a gate electrode formed on the GaN-based semiconductor layer, current blocking regions formed in portions of the SiC drift layer and located below the source and gate electrodes, and a drain electrode formed on a surface that opposes the GaN-based semiconductor layer across the SiC layer.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 25, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Takeshi Kawasaki, Ken Nakata, Seiji Yaegashi
  • Patent number: 7713765
    Abstract: A method for manufacturing a semiconductor device having a compound semiconductor layer that is provided on a substrate and includes a cladding layer of a first conductivity type, an activation layer, a cladding layer of a second conductivity type that is the opposite of the first conductivity type, includes the steps of: forming a diffusion source layer on the compound semiconductor layer; forming a first diffusion region in the compound semiconductor layer by carrying out a first heat treatment, so that the first diffusion region includes a light emitting facet for emitting light from the activation layer; removing the diffusion source layer; forming a first SiN film having a refractive index of 1.9 or higher on the compound semiconductor layer; and turning the first diffusion region into the second diffusion region by carrying out a second heat treatment.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: May 11, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Takeshi Sakashita, Masanori Saito
  • Patent number: 7710083
    Abstract: An electronic device includes a DC/DC converter supplied with an external power supply, and an electronic circuit having a power supply input to which an output of the DC/DC converter is supplied. A converted voltage that is the output of the DC/DC converter is lower than a center value of a recommended operating condition for a voltage of the power supply input of the electronic circuit.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: May 4, 2010
    Assignee: Eudyna Devices Inc.
    Inventor: Shingo Inoue
  • Patent number: 7701984
    Abstract: A laser module has an optical amplifier, a first etalon and a wavelength selectable mirror. The first etalon has wavelength peaks at a given wavelength interval in transmission characteristics and transmits a light from the optical amplifier. The wavelength peaks are tunable. The wavelength selectable mirror acts as an external mirror of an external cavity laser including the optical amplifier, and has a relatively high reflection intensity at a part of wavelength range in an effective gain range of the optical amplifier. The effective gain range of the optical amplifier includes more than one wavelength peak of the first etalon. A reflection bandwidth where the wavelength selectable mirror has a relatively high reflection intensity is less than twice of the wavelength interval of the wavelength peaks of the first etalon.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: April 20, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Toshio Higashi, Yasuyuki Yamauchi, Emmanuel le Taillandier de Gabory, Hirokazu Tanaka, Junji Watanabe
  • Publication number: 20100091805
    Abstract: An optical semiconductor device includes an optical semiconductor element, a metal pattern and at least one thermal conductive material. The optical semiconductor element has a first optical waveguide region and a second optical waveguide region. The second optical waveguide region is optically coupled to the first optical waveguide region and has a heater for changing a refractive index of the second optical waveguide region. The metal pattern is provided on an area to be thermally coupled to a temperature control device. The thermal conductive material couples the metal pattern with an upper face of the first optical waveguide region of the optical semiconductor element. The thermal conductive material is electrically separated from the first optical waveguide region.
    Type: Application
    Filed: December 17, 2009
    Publication date: April 15, 2010
    Applicant: EUDYNA DEVICES INC.
    Inventors: Tsutomu Ishikawa, Takuya Fujii
  • Patent number: 7696593
    Abstract: A semiconductor photo detecting element includes a PIN-type photo detecting element and window semiconductor layer. The PIN-type photo detecting element has a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer is provided on the semiconductor substrate, is lattice-matched to the semiconductor substrate, includes a first conductivity type dopant, and has first band gap energy. The second semiconductor layer is provided on the first semiconductor layer, has the first band gap energy, and has a concentration of the first conductivity type dopant lower than that of the first semiconductor layer or is substantially undoped. The third semiconductor layer is provided on the second semiconductor layer. The window semiconductor layer has second band gap energy larger than the first band gap energy at a light-incoming side with respect to the second semiconductor layer and has a thickness of 5 nm to 50 nm.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 13, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Yoshihiro Yoneda, Ryuji Yamabi
  • Patent number: 7692227
    Abstract: A semiconductor device has an electrode pad, a capacitor and a substrate. The substrate has a given area on which the electrode pad and the capacitor are arranged. The electrode pad and the capacitor are arranged on the substrate so that each of at least two sides of the capacitor and each of at least two sides of the electrode pad is adjacent to each other at a given interval. The capacitor has a connecting side that connects the two sides of the capacitor and faces to the electrode pad. Outside angles of the capacitor formed by the connecting side and the two sides of the capacitor are more than 90 degrees.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: April 6, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Ryuji Yamabi, Hiroshi Yano
  • Publication number: 20100081241
    Abstract: A semiconductor device includes an operating layer made of a semiconductor and a silicon nitride film formed on the operating layer with the use of a mixed gas that includes mono-silane gas, hydrogen gas, and nitrogen gas, by a plasma CVD apparatus, under a condition that a flow rate of the hydrogen gas is 0.2 percent to 5 percent to an overall flow rate.
    Type: Application
    Filed: December 4, 2009
    Publication date: April 1, 2010
    Applicant: EUDYNA DEVICES INC.
    Inventor: Norikazu IWAGAMI
  • Patent number: 7671680
    Abstract: An electronic circuit includes an input terminal, a transimpedance amplifier connected to the input terminal and including an amplifier and a feedback resistor, a first time constant circuit smoothing an output from the transimpedance amplifier, a gain control circuit arranged between the input terminal and ground potential and controlling current flowing between the input terminal and the ground potential on the basis of the output from the first time constant circuit, and a safeguard circuit controlling the gain control circuit and blocking the current flowing between the input terminal and the ground potential, when a signal to be input into the input terminal is stopped.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: March 2, 2010
    Assignee: Eudyna Devices Inc.
    Inventor: Hiroshi Hara
  • Publication number: 20100040101
    Abstract: An optical semiconductor device has a semiconductor substrate, a semiconductor region and heater. The semiconductor region has a stripe shape demarcated with a top face and a side face thereof. The stripe shape has a width smaller than a width of the semiconductor substrate. An optical waveguide layer is located in the semiconductor region. A distance from a lower end of the side face of the semiconductor region to the optical waveguide layer is more than half of the width of the semiconductor region. The heater is provided above the optical waveguide layer.
    Type: Application
    Filed: October 1, 2009
    Publication date: February 18, 2010
    Applicant: EUDYNA DEVICES, INC.
    Inventor: Tsutomu Ishikawa
  • Patent number: 7663228
    Abstract: An electronic component includes an electronic element, a conductive first base portion, a conductive second base portion, an insulator and a terminal. An electronic element is to be mounted on the electronic element mounting portion. The electronic element mounting portion is mounted on the first base portion. The insulator insulates the first base portion from the second base portion and couples the first base portion to the second base portion. The terminal is provided on the first base portion and is insulated from the first base portion.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: February 16, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Yoshihiro Tateiwa, Kakushi Nakagawa
  • Publication number: 20100034224
    Abstract: A tunable laser module includes a tunable laser section including a gain medium and a wavelength filter having a periodic characteristic which brings about a discontinuous variation of an oscillation wavelength, and a monitoring section adapted to output a monitoring signal which periodically varies in response to the oscillation wavelength of the tunable laser section. The monitoring section includes a monitoring wavelength filter having a periodic characteristic which defines the monitoring signal. The relationship between the period of the wavelength filter and the period of the monitoring wavelength filter is set such that the monitoring signal varies when the oscillation wavelength varies discontinuously.
    Type: Application
    Filed: August 4, 2009
    Publication date: February 11, 2010
    Applicants: FUJITSU LIMITED, EUDYNA DEVICES INC.
    Inventors: Kazumasa Takabayashi, Tsutomu Ishikawa, Hirokazu Tanaka
  • Patent number: 7656927
    Abstract: An optical semiconductor device includes an optical semiconductor element, a metal pattern and at least one thermal conductive material. The optical semiconductor element has a first optical waveguide region and a second optical waveguide region. The second optical waveguide region is optically coupled to the first optical waveguide region and has a heater for changing a refractive index of the second optical waveguide region. The metal pattern is provided on an area to be thermally coupled to a temperature control device. The thermal conductive material couples the metal pattern with an upper face of the first optical waveguide region of the optical semiconductor element. The thermal conductive material is electrically separated from the first optical waveguide region.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: February 2, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Tsutomu Ishikawa, Takuya Fujii
  • Publication number: 20100022044
    Abstract: A semiconductor laser has first and second diffractive grating regions. The first diffractive grating region has segments, has a gain, and has first discrete peaks of a reflection spectrum. The second diffractive grating region has segments combined to each other, and has second discrete peaks of a reflection spectrum. Each segment has a diffractive grating and a space region. Pitches of the diffractive grating are substantially equal to each other. A wavelength interval of the second discrete peaks is different from that of the first discrete peaks. A part of a given peak of the first discrete peaks is overlapped with that of the second discrete peaks when a relationship between the given peaks of the first discrete peaks and the second discrete peaks changes.
    Type: Application
    Filed: October 7, 2009
    Publication date: January 28, 2010
    Applicant: EUDYNA DEVICES INC.
    Inventor: Takuya FUJII
  • Patent number: 7648867
    Abstract: A method for fabricating a semiconductor device includes: forming a dummy gate that defines a region in which a gate electrode should be formed on a semiconductor substrate; forming a surface film on the semiconductor substrate by directional sputtering vertical to a surface of the semiconductor substrate, the directional sputtering being one of collimate sputtering, long throw sputtering and ion beam sputtering; removing the surface film formed along a sidewall of the dummy gate; removing the dummy gate; and forming the gate electrode in the region from which the dummy gate on the semiconductor substrate has been removed.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: January 19, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Masataka Watanabe, Hiroshi Yano
  • Patent number: 7644326
    Abstract: A testing system includes a plurality of test applying portions and a plurality of testing portions, each test applying portion having a test device that generates an output signal and each testing portion tests the output signal of the test device, in response to the test applying portion. The testing system further includes a switch portion that switches the output signal of the test device between the test applying portions and the testing portions. The switch portion includes, a first switch having an input port and a plurality of output ports, which selects the output port for connecting the input port, a second switch having a plurality of input ports and an output port, which selects the input port for connecting the output port, and a connecting portion that has a plurality of transmission parts that connect the output ports of the first switch and the input ports of the second switch.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: January 5, 2010
    Assignee: Eudyna Devices Inc.
    Inventor: Haruyoshi Ono