Patents Assigned to Eudyna Devices Inc.
  • Patent number: 7629187
    Abstract: A fabrication method of a semiconductor luminescent device includes forming a compound semiconductor layer having a structure in which a first conductivity-type clad layer, an active layer, a second conductivity-type clad layer are layered in order on a substrate, the second conductivity-type being different from the first conductivity-type and forming a low-refractive-index region in a waveguide in an area to be an end face from which an output light from the waveguide in the compound semiconductor layer is emitted, the low-refractive-index region having an equivalent refractive-index lower than that of another area in the waveguide. The step of forming the low-refractive-index region includes determining a width of the low-refractive-index region in a longitudinal direction of the waveguide so that an emission angle of the output light of the semiconductor luminescent device is controlled to be a desirable value, and forming the low-refractive-index region having the width.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: December 8, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Hiroyuki Sumitomo, Satoshi Kajiyama, Makoto Ueda
  • Patent number: 7620093
    Abstract: A semiconductor laser has first and second diffractive grating regions. The first diffractive grating region has segments, has a gain, and has first discrete peaks of a reflection spectrum. The second diffractive grating region has segments combined to each other, and has second discrete peaks of a reflection spectrum. Each segment has a diffractive grating and a space region. Pitches of the diffractive grating are substantially equal to each other. A wavelength interval of the second discrete peaks is different from that of the first discrete peaks. A part of a given peak of the first discrete peaks is overlapped with that of the second discrete peaks when a relationship between the given peaks of the first discrete peaks and the second discrete peaks changes.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: November 17, 2009
    Assignee: Eudyna Devices Inc.
    Inventor: Takuya Fujii
  • Patent number: 7614801
    Abstract: An optical axis adjusting method for adjusting a tilt angle of an optical axis in two regions optically coupled in a holding member includes the steps of: roughly adjusting the optical axis by irradiating a first region on the holding member with a laser beam; and finely adjusting the optical axis by irradiating a second region on the holding member with a laser beam. One of the two regions is set as a reference point. The first region is located closer to the reference point, while the second region is located further from the reference point.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: November 10, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Haruyoshi Ono, Hidemitsu Sugawara
  • Patent number: 7609070
    Abstract: A manufacturing method of an electronic device includes applying a direct voltage having a first polarity to a capacitor that has an insulating layer including nitrogen and silicon as a capacitor dielectric layer, testing the capacitor to which the direct voltage having the first polarity is applied and determining a nondefective capacitor and a defective capacitor, and applying a direct voltage having a second polarity to the nondefective capacitor. The second polarity is opposite to the first polarity.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: October 27, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Tomohiro Kagiyama, Yasuhiro Tosaka, Norikazu Iwagami
  • Patent number: 7604418
    Abstract: An optical communication module includes a receptacle, a chassis and a pressing jig. The receptacle has a photonic device therein and a projection portion. The chassis houses the receptacle. The pressing jig has an engage portion. The engage portion is latched with the chassis with the pressing jig pressing the projection portion of the receptacle to the chassis.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: October 20, 2009
    Assignee: Eudyna Devices Inc.
    Inventor: Masato Hino
  • Patent number: 7603019
    Abstract: There is provided an optical communication module including a receptacle that has an optical element therein and a brim portion, a chassis on which the receptacle is mounted, and a jig into which the receptacle is inserted, that has an opening smaller than the brim portion, and that presses the brim portion to the chassis.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: October 13, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Masato Hino, Shinya Suzuki
  • Patent number: 7592647
    Abstract: A semiconductor device includes a GaN-based semiconductor layer that is formed on a substrate and an opening region, an electron conduction layer formed on an inner surface of the opening region, an electron supply layer that has a larger band gap than the electron conduction layer and is formed on the electron conduction layer disposed on the inner surface of the opening region, and a gate electrode formed on a side surface of the electron supply layer in the opening region. A source electrode is formed on the GaN-based semiconductor layer. A drain electrode is connected to a surface of the GaN-based semiconductor layer opposite to the source electrode.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: September 22, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Ken Nakata, Takeshi Kawasaki, Seiji Yaegashi
  • Patent number: 7585779
    Abstract: A fabrication method of a semiconductor device includes steps of performing any one of O2 ashing, organic processing, and dry etching on a surface of a GaN-based semiconductor layer, etching the surface of the GaN-based semiconductor layer in a mixed solution of acid and an oxidizing agent, and forming an electrode on the surface of the GaN-based semiconductor layer.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: September 8, 2009
    Assignee: Eudyna Devices Inc.
    Inventor: Masahiro Nishi
  • Patent number: 7585120
    Abstract: An optical device includes: a first optical component that has an end face oblique with respect to a plane perpendicular to an optical axis; a second optical component that is optically coupled to the first optical component; and a lens that is placed between the first optical component and the second optical component, and is positioned so that the trajectory of a focal point formed when the first optical component and the second optical component rotate relative to each other falls within a valid region on the surface of the second optical component.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: September 8, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Makoto Ito, Sosaku Sawada
  • Patent number: 7579915
    Abstract: An electronic circuit includes: a control circuit that controls the gain of a transimpedance amplifier by taking part of an input current to be input to the transimpedance amplifier, based on the output voltage of the transimpedance amplifier; and a PIN diode that is provided between an input of the transimpedance amplifier and the control circuit, and is connected in the forward direction with respect to the current to be drawn into the control circuit.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: August 25, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Taizou Tatsumi, Sosaku Sawada
  • Patent number: 7561001
    Abstract: An electronic circuit device includes a negative resistance generating circuit, a second transistor and a path. The negative resistance generating circuit has a first transistor having a control terminal coupled to a resonator. The second transistor has a control terminal coupled to an output terminal of the first transistor and has an output terminal coupled to a DC bias terminal. The path is coupled to between the DC bias terminal and an output terminal of the first transistor through the second transistor and provides a bias to the first transistor.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: July 14, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Tsuneo Tokumitsu, Osamu Baba
  • Patent number: 7561853
    Abstract: A switch that selectively changes radio frequency signals includes at least three FETs, which are connected in series. The source electrodes or drain electrodes arranged at an intermediate stage have a width narrower than that of the source electrodes or the drain electrodes arranged at the initial and final stages. It is thus possible to lower the parasitic capacitance to ground at the intermediate stage and to thereby realize the switch having a high handling power.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: July 14, 2009
    Assignee: Eudyna Devices Inc.
    Inventor: Naoyuki Miyazawa
  • Patent number: 7560346
    Abstract: A semiconductor device includes: a first FET that is formed with first unit FETs each having a first finger electrode and a second finger electrode provided on either side of a gate finger electrode, the first unit FETs being connected in parallel; and a second FET that is formed with second unit FETs each having a first finger electrode and a second finger electrode provided on either side of a gate finger electrode, the second unit FETs being connected in parallel. In this semiconductor device, the second finger electrode of each of the first unit FETs and the first finger electrode of each corresponding one of the second unit FETs form a common finger electrode, and the first finger electrodes of the first unit FETs, the second finger electrodes of the second unit FETs, and the common finger electrodes are arranged in the gate length direction of the first FET and the second FET.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: July 14, 2009
    Assignee: Eudyna Devices Inc.
    Inventor: Takeshi Igarashi
  • Publication number: 20090176352
    Abstract: A semiconductor device includes a substrate, a buffer layer that is formed with an aluminum nitride layer on the substrate and has a film thickness of 5 nm to 40 nm, an operating layer that is formed with a gallium nitride-based semiconductor on the buffer layer, and a control electrode that is formed on the operating layer.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 9, 2009
    Applicants: EUDYNA DEVICES, INC., FUJITSU LIMITED
    Inventors: Mitsunori Yokoyama, Kenji Imanishi, Toshihide Kikkawa
  • Publication number: 20090168817
    Abstract: A testing method of a wavelength-tunable laser having a resonator including wavelength selection portions having wavelength property different from each other includes a first step of controlling the wavelength-tunable laser so as to oscillate at a given wavelength according to an initial setting value, a second step of tuning the wavelength property of the wavelength selection portions and detecting discontinuity point of gain-condition-changing of the wavelength-tunable laser, and a third step of obtaining a stable operating point of the wavelength selection portion according to a limiting point of an oscillation condition at the given wavelength, the limiting point being a point when the discontinuity point is detected.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 2, 2009
    Applicant: EUDYNA DEVICES INC.
    Inventors: Tsutomu Ishikawa, Toyotoshi Machida, Hirokazu Tanaka
  • Patent number: 7550831
    Abstract: An electronic device has a substrate, a conductive layer and a substrate mounted portion. The substrate has a circuit portion used from 60 GHz to 80 GHz. The conductive layer is provided directly on a face of the substrate that is opposite side of the circuit portion. The face having the circuit portion of the substrate is mounted face down on the substrate mounted portion. A thickness of the conductive layer is a thickness where a sheet resistance of the conductive layer is ΒΌ to 4 times of a resistance component of an impedance of the substrate.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: June 23, 2009
    Assignee: Eudyna Devices Inc.
    Inventor: Mitsuji Nunokawa
  • Patent number: 7550398
    Abstract: A semiconductor device includes a silicon nitride (SiN) film provided on a crystal surface of a nitride semiconductor, the SiN film having a hydrogen content equal to or smaller than 15 percent.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: June 23, 2009
    Assignee: Eudyna Devices, Inc.
    Inventors: Masahiro Tanaka, Tsutomu Komatani
  • Patent number: 7539385
    Abstract: An optical semiconductor, includes a semiconductor substrate having a (100) principal surface, a waveguide mesa stripe formed on a first region of the semiconductor substrate, the waveguide mesa stripe guiding a light therethrough; a plurality of dummy mesa patterns formed on the semiconductor substrate in a second region at a forward side of the first region, and a semi-insulating buried semiconductor layer formed on the semiconductor substrate so as to cover the first and second regions continuously, the semi-insulating buried semiconductor layer filling a right side and a left side of the waveguide mesa stripe in the first region and a gap between the plurality of dummy mesa patterns in the second region.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 26, 2009
    Assignees: Fujitsu Limited, Eudyna Devices Inc.
    Inventors: Ayahito Uetake, Tatsuya Takeuchi
  • Patent number: 7532085
    Abstract: An electronic device includes a first transmission line, a second transmission line and a ground-coupling portion. The first transmission line is composed of a first signal line transmitting a given high frequency wave signal and a first ground. The second transmission line is composed of a second signal line transmitting the high frequency wave signal and a second ground. The ground-coupling portion couples the first ground and the second ground. A phase difference between the high frequency wave signals at both ends of the ground-coupling portion is substantially integral multiple of 180 degrees.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: May 12, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Tsuneo Tokumitsu, Hideki Tango, Osamu Anegawa
  • Publication number: 20090103585
    Abstract: An optical semiconductor device includes an optical semiconductor element, a metal pattern and at least one thermal conductive material. The optical semiconductor element has a first optical waveguide region and a second optical waveguide region. The second optical waveguide region is optically coupled to the first optical waveguide region and has a heater for changing a refractive index of the second optical waveguide region. The metal pattern is provided on an area to be thermally coupled to a temperature control device. The thermal conductive material couples the metal pattern with an upper face of the first optical waveguide region of the optical semiconductor element. The thermal conductive material is electrically separated from the first optical waveguide region.
    Type: Application
    Filed: December 9, 2008
    Publication date: April 23, 2009
    Applicant: EUDYNA DEVICES, INC.
    Inventors: Tsutomu Ishikawa, Takuya Fujii