Patents Assigned to Fairchild Semiconductor Corporation
  • Publication number: 20190181083
    Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.
    Type: Application
    Filed: February 19, 2019
    Publication date: June 13, 2019
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina ESTACIO
  • Publication number: 20190181763
    Abstract: In one embodiment, a power supply controller, or alternately a semiconductor device having a power supply controller, may have a first circuit configured to form a sense signal that is representative of a signal from an auxiliary winding of a transformer. A feedback circuit may be configured to allow the sense signal to increase in response to a turn-off of the power switch, to subsequently detect a second increase of the sense signal prior to subsequently turning on the power switch, and to form a feedback signal as a value of the sense signal responsively to the second increase of the sense signal.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 13, 2019
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Zhibo TAO, Chih-Hsien HSIEH, Yue-Hong TANG
  • Publication number: 20190181765
    Abstract: A switched-mode power supply with near valley switching includes a quasi-resonant converter. The converter includes a switch element that is turned on not only at the valley, but also in a window range of ?tNVW close to the valley, where the voltage across the switch element is at its minimum. This advantageously reduces switching loss and maintains a balance between efficiency and frequency variation.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 13, 2019
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Zhibo TAO, Jung-Sheng CHEN, Li LIN, Kai-Fang WEI, Chih-HSIEN HSIEH, Hangseok CHOI, Yue-Hong TANG
  • Patent number: 10318394
    Abstract: A port controller includes an advertise block configured to determine a cable assembly coupled to the port controller is not compliant with a standard used by the port controller, a comparator configured to determine a current drawn from a power converter coupled to the cable assembly exceeds a capability of the power converter based on comparing a bus voltage to a threshold voltage, and a protection block configured to, in response to determining the current drawn from the power converter exceeds the capability of the power converter, cause the current drawn from the power converter to be reduced.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 11, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William Robert Newberry
  • Patent number: 10291052
    Abstract: In accordance with an embodiment, a bypass charging circuit includes a pair of transistors having current carrying terminals commonly connected to form a node. An input of a comparator is coupled to the node through a switch and to a resistor. Another input terminal of the comparator is coupled for receiving a reference voltage. Optionally, a transistor may be connected to the bypass charging circuit. In accordance with another embodiment a method is provided in which bypass charging transistors are coupled to first input of a comparator in response to closing a switch. A voltage is generated at the first input of the comparator in response to closing the switch and the voltage is compared with a reference voltage. In response to the comparison, a status indicator signal is generated to indicate the presence of a low-impedance failure in one or both of the bypass charging transistors.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 14, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: James A. Meacham, II, Karttikeya Shah
  • Patent number: 10270438
    Abstract: A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its bulk.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: April 23, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Lei Huang, Na Meng, Kenneth P. Snowdon
  • Patent number: 10256735
    Abstract: A switched-mode power supply with near valley switching includes a quasi-resonant converter. The converter includes a switch element that is turned on not only at the valley, but also in a window range of ?tNVW close to the valley, where the voltage across the switch element is at its minimum. This advantageously reduces switching loss and maintains a balance between efficiency and frequency variation.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 9, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Zhibo Tao, Jung-Sheng Chen, Li Lin, Kai-Fang Wei, Chih-Hsien Hsieh, Hangseok Choi, Yue-Hong Tang
  • Patent number: 10256178
    Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 9, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
  • Patent number: 10236779
    Abstract: In one embodiment, a power supply controller, or alternately a semiconductor device having a power supply controller, may have a first circuit configured to form a sense signal that is representative of a signal from an auxiliary winding of a transformer. A feedback circuit may be configured to allow the sense signal to increase in response to a turn-off of the power switch, to subsequently detect a second increase of the sense signal prior to subsequently turning on the power switch, and to form a feedback signal as a value of the sense signal responsively to the second increase of the sense signal.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 19, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Zhibo Tao, Chih-Hsien Hsieh, Yue-Hong Tang
  • Patent number: 10190919
    Abstract: In a general aspect, a circuit can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance and a temperature information circuit. The temperature information circuit can be configured to: receive a first voltage from the first terminal of the temperature-sensitive resistance; receive a second voltage from the second terminal of the temperature-sensitive resistance; and provide temperature information based on the first voltage and the second voltage. The temperature information circuit can include a first comparison circuit configured to determine a difference between the first voltage and the second voltage, and a second comparison circuit configured to compare an output of the first comparison circuit to a reference.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: January 29, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Roy Yarbrough
  • Publication number: 20190013729
    Abstract: A Power Factor Correction (PFC) circuit includes an oscillator circuit. The oscillator circuit receives a valley detect signal indicating a zero current condition, determines a blanking time according to an operational cycle of the PFC circuit, and determines to initiate the operational cycle according to the valley detect signal and the blanking time. Determining the blanking time includes selecting one of a plurality of predetermined blanking times according to a count of operational cycles of the PFC circuit. The PFC circuit may operate in a Boundary Conduction Mode or a Discontinuous Conduction Mode depending on whether a charge-discharge period is greater than the blanking time. The PFC circuit may determine, according to its output voltage, a first duration of a charging period, determine a delay time according to zero current times of previous operational cycles, and extend the first duration of the charging period by the delay time.
    Type: Application
    Filed: August 30, 2018
    Publication date: January 10, 2019
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Jintae KIM, Sangcheol MOON, Hangseok CHOI
  • Patent number: 10145352
    Abstract: In a general aspect, an ignition circuit can include a control circuit configured to receive a command signal from an engine control unit, and a driving circuit coupled with the control circuit. The driving circuit can be configured to be coupled with a resonant circuit that includes a primary winding of an ignition coil. The control circuit and the driving circuit can be configured, in response to a command signal, to drive the resonant circuit at a first frequency to generate a voltage in the ignition coil to initiate a spark in a spark plug; and, in response to the spark being initiated in the spark plug, drive the resonant circuit at a second frequency to maintain the spark in the spark plug for combustion of a fuel mixture. The control circuit can be configured to, after the combustion of the fuel mixture, to disable the driving circuit.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: December 4, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Qingquan Tang
  • Patent number: 10148188
    Abstract: An active clamp flyback controller includes first and second input terminals, a clamp voltage detection circuit, and an overvoltage protection circuit. The first input terminal is adapted to be coupled to a terminal of a clamp capacitor. The second input terminal receives a feedback signal proportional to a voltage across an auxiliary winding of a flyback transformer. The clamp voltage detection circuit is coupled to the first and second input terminals, and detects a clamp voltage as a difference between a voltage at the first input terminal and an input voltage, the clamp voltage detection circuit calculating the input voltage using a signal from the second input terminal. The overvoltage protection circuit is coupled to the clamp voltage detection circuit for comparing the clamp voltage to a threshold and triggering a protection operation if the clamp voltage is greater than the threshold.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 4, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Gwanbon Koo, Dibyendu Rana
  • Publication number: 20180342576
    Abstract: In at least one general aspect, a silicon carbide (SiC) device can include a drift region and a termination region at least partially surrounding the SiC device. The termination region can have a first transition zone and a second transition zone. The first transition zone can be disposed between a first zone and a second zone, and the second zone can have a top surface lower in depth than a depth of a top surface of the first zone. The first transition zone can have a recess, and the second transition zone can be disposed between the second zone and a third zone.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 29, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Andrei KONSTANTINOV
  • Patent number: 10142751
    Abstract: This document discusses, among other things, systems and methods to reduce power use of an accessory detection device. The accessory detection device can be configured to be coupled to a mobile device having an audio jack configured to be coupled to a mobile device accessory having a send/end key. In an example, the accessory detection device can include a comparator and a switch. The comparator can be configured to receive mobile device accessory information from the mobile device accessory and to determine activation of the send/end key using the received mobile device accessory information. The switch can be configured to receive connection information indicative of mobile device accessory connection to the audio jack and to isolate a reference input of the comparator from a supply voltage using the connection information, for example, to reduce leakage current.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: November 27, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Seth M. Prentice, Julie Lynn Stultz
  • Patent number: 10116202
    Abstract: A DC/DC power supply system includes a primary side and a secondary side to generate an output DC voltage from an input DC voltage. The power supply also includes adaptive clamping circuitry that generates an adjustable clamping voltage and/or current to limit a Vds breakdown voltage for switches of the secondary side.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: October 30, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Xiaopeng Wang, Kaiwei Yao
  • Patent number: 10097084
    Abstract: Systems and methods are disclosed, including, for example, a low-voltage control circuit configured to receive a charge pump voltage, a rail voltage, and a switch control signal, to provide the charge pump voltage when the switch control signal is in a first state, and to provide the higher of the charge pump voltage and the rail voltage when the switch control signal is in a second state. The system can include a first pick-high circuit configured to receive the rail voltage and the charge pump voltage, and to provide the higher of the rail voltage and the charge pump voltage at an output. The switch control signal, in the first state, can include the output of the pick-high circuit. Methods of forming such apparatus are disclosed, as well as methods of operation, and other embodiments.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: October 9, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Julie Lynn Stultz
  • Patent number: 10090695
    Abstract: This document discusses, among other things, apparatus and methods to optimize charging of a battery, including providing a first charge profile configured to provide charge current pulses to a battery in a plurality of steps. In the first charge profile, the charge current pulses can be stepped down in the plurality of steps using a comparison of a terminal voltage of the battery to a clamp voltage. When the terminal voltage meets or exceeds the clamp voltage, a high time current of the charge current pulse can be decreased and the clamp voltage can be increased before providing a subsequent charge current pulse.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: October 2, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert A. Card, Ming Chuen Alvan Lam
  • Patent number: 10090757
    Abstract: A Power Factor Correction (PFC) circuit includes an oscillator circuit. The oscillator circuit receives a valley detect signal indicating a zero current condition, determines a blanking time according to an operational cycle of the PFC circuit, and determines to initiate the operational cycle according to the valley detect signal and the blanking time. Determining the blanking time includes selecting one of a plurality of predetermined blanking times according to a count of operational cycles of the PFC circuit. The PFC circuit may operate in a Boundary Conduction Mode or a Discontinuous Conduction Mode depending on whether a charge-discharge period is greater than the blanking time. The PFC circuit may determine, according to its output voltage, a first duration of a charging period, determine a delay time according to zero current times of previous operational cycles, and extend the first duration of the charging period by the delay time.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: October 2, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Jintae Kim, Sangcheol Moon, Hangseok Choi
  • Publication number: 20180269302
    Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epitaxial layer disposed on the SiC substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region. The gate trench can have a depth that is greater than a depth of the well region and less than a depth of the epitaxial layer. The device can include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k material and a second high-k dielectric material that is different than the first high-k dielectric material. The device can include a conductive gate electrode disposed on the hybrid gate dielectric.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Salman AKRAM, Venkat ANANTHAN