Patents Assigned to Faraday Technology Corp.
  • Patent number: 11005468
    Abstract: A method for performing duty-cycle correction of an output clock in a Double Data Rate (DDR) system includes: setting a fixed delay of a rising-edge of the output clock as a parameter X which is equal to a digital Master Delay Locked Loop (MDLL) code of the DDR system multiplied by a percentage representing an estimated distortion of the duty-cycle of the output clock from a desired duty-cycle; shifting the rising-edge of the output clock by the fixed delay; and determining whether a duty cycle of the shifted output clock meets the desired duty-cycle. When a duty-cycle of the shifted output clock meets the desired duty-cycle, the fixed rising-edge delay is taken as a final delay code for the output clock; otherwise, a falling-edge of the output clock is shifted by an amount in a range between 0 and NX, wherein N is an integer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 11, 2021
    Assignee: Faraday Technology Corp.
    Inventors: Sivaramakrishnan Subramanian, Sridhar Cheruku, Sandeep Kumar Mohanta, Hussainvali Shaik
  • Publication number: 20210066286
    Abstract: The electrostatic discharge (ESD) protection apparatus includes a first well, a second well, a first doping region, and a second doping region. The first well is disposed in a substrate having a first conductivity type, wherein the first well has a second conductivity type and the substrate is electrically connected to a first pad. The second well is disposed in the first well, wherein the second well has the first conductivity type. The first doping region is disposed in the second well, wherein the first doping region has the second conductivity type, and the first doping region is electrically connected to a second pad. The second doping region is disposed in the second well, wherein the second doping region has the first conductivity type.
    Type: Application
    Filed: January 17, 2020
    Publication date: March 4, 2021
    Applicant: Faraday Technology Corp.
    Inventors: Chia-Ku Tsai, Tsung-Hsiao Lin
  • Patent number: 10924089
    Abstract: A comparing circuit and a comparing module with hysteresis are provided. The comparing module includes a first resistor, a second resistor, and the comparing circuit, which are electrically connected to each other. A comparison voltage is determined according to an input voltage and the resistances of the first resistor and the second resistor. The comparing circuit includes an input circuit, an eternal circuit, and a coupling module. The coupling module includes a first coupling transistor, a second coupling transistor, a third transistor, and a fourth coupling resistor. Control terminals of the first coupling transistor and the second coupling transistor are selectively electrically connected to either one of a first terminal and a second terminal. The second terminals of the third coupling transistor and the fourth coupling transistor are selectively electrically connected to either one of the first terminal and the second terminal.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 16, 2021
    Assignees: FARADAY TECHNOLOGY CORPORATION, Faraday Technology Corp.
    Inventors: Xiao-Dong Fei, Wei Wang, San-Yueh Huang
  • Patent number: 10855437
    Abstract: The present invention provides a clock data recovery apparatus and an operation method thereof. The clock data recovery apparatus includes an equalizer, a phase detector, a charge pump, and an oscillation circuit. The equalizer is configured to equalize raw data to generate equalized data. The phase detector is coupled to the equalizer to receive the equalized data. The phase detector is configured to generate a detection result according to the equalized data. The phase detector performs pattern-filtering on the equalized data to filter out at least one pattern. The charge pump is coupled to the phase detector to receive the detection result. The charge pump is configured to generate a control signal according to the detection result. The oscillation circuit is coupled to the charge pump to receive the control signal. The oscillation circuit is configured to generate a clock signal according to the control signal.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 1, 2020
    Assignees: FARADAY TECHNOLOGY CORPORATION, Faraday Technology Corp.
    Inventors: Ling Chen, Andrew Chao, Xiao-Dong Fei, Wei Liu
  • Patent number: 10833674
    Abstract: A switch device including a switch circuit and switch controller. The switch circuit comprises first and second switches to selectively enable a path between an input terminal and an output terminal. The switch controller refers to a selection signal and a switch signal to respectively generate a first switch control signal at a first switch control signal output terminal and a second switch control signal at a second switch control signal output terminal. When the voltage level of an input signal at the input terminal is larger than a power voltage, the switch controller generates the first switch control signal and the second switch control signal capable of turning off the switch circuit. When the voltage level of the input signal is not larger than the power voltage, the switch controller generates the first switch control signal and the second switch control signal according to the switch signal.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Feng Xu, Shu Dong Wu, Zhen Liang Zhang
  • Patent number: 10812057
    Abstract: A time detection circuit and a time detection method are provided. The time detection circuit includes an input signal processor and a time signal amplifier. The input signal processor receives a first input signal and a second input signal, calculates a time difference value between the first input signal and the second input signal, adjusts the time difference value by comparing the time difference value with a set reference value, and provides the adjusted time difference value. The time signal amplifier receives the adjusted time difference value, and amplifies the adjusted time difference value to generate an amplified time signal. The time signal amplifier operates in a linear operation region between a first time value and a second time value, and the set reference value is set according to the first time value and the second time value.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: October 20, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Pei-Yuan Chou, Jinn-Shyan Wang, Chuen-Shiu Chen
  • Patent number: 10811899
    Abstract: A power switching circuit receives a first power, a second power and a switching signal, and generates an output power. The power switching circuit includes a first power path and a second power path. The first power path is connected with the first power. The second power path is connected with the second power. When the switching signal in a logic high level, the first power path is in a conducting state and the second power path is in a non-conducting state. Consequently, the first power is selected as the output power by the power switching circuit. When the switching signal in a logic low level, the first power path is in the non-conducting state and the second power path is in the conducting state. Consequently, the second power is selected as the output power by the power switching circuit.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: October 20, 2020
    Assignees: FARADAY TECHNOLOGY CORPORATION, Faraday Technology Corp.
    Inventors: Xiao-Dong Fei, Zheng-Xiang Wang, Song-Rong Han, Wei Wang
  • Patent number: 10797683
    Abstract: A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 6, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Vinod Kumar Jain, Chi-Yeu Chao, Prateek Kumar Goyal, Han-Kyul Lim
  • Patent number: 10756674
    Abstract: An amplifier including a first routing circuit, an input stage circuit, an output stage circuit, a second routing circuit, and a bias voltage generating circuit is provided. The bias voltage generating circuit generates a first bias voltage and a second bias voltage for respectively supplying a first tail current source and a second tail current source of the input stage circuit. During a first period, the first bias voltage is related to the voltage at a first input terminal of the amplifier, and the second bias voltage is related to the voltage at a second input terminal of the amplifier. During a second period, the first bias voltage is related to the voltage at the second input terminal of the amplifier, and the second bias voltage is related to the voltage at the first input terminal of the amplifier.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: August 25, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Hsu-Ming Tsai, Ta-Wei Wang
  • Patent number: 10749508
    Abstract: A signal converter, a duty-cycle corrector, and a differential clock generator are provided. The differential clock generator includes the signal converter and the duty-cycle corrector. The signal converter is capable of calibrating skew distortion, and the duty-cycle corrector is capable of calibrating duty-cycle distortion. With the signal converter and the duty-cycle corrector, the differential clock generator can be applied to communication devices operating at high frequency.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 18, 2020
    Assignee: Faraday Technology Corp.
    Inventor: Vinod Kumar Jain
  • Publication number: 20200242058
    Abstract: An interrupt management system and a management method thereof are provided. The interrupt management system includes a processor and an interrupt signal expanding controller. The processor receives a plurality of original interrupt signals. The interrupt signal expanding controller includes a decoder and an interrupt vector table. The decoder receives a plurality of expanding interrupt request signals, and decodes the expanding interrupt request signals to generate the original interrupt signals, where number of the expanding interrupt request signals is larger than number of the original interrupt signals. The interrupt vector table stores a plurality of interrupt vectors. The decoder reads one of the interrupt vectors to obtain an accessed interrupt vector according to the expanding interrupt request signals, and the interrupt signal expanding controller transmits the accessed interrupt vector to the processor.
    Type: Application
    Filed: June 3, 2019
    Publication date: July 30, 2020
    Applicant: Faraday Technology Corp.
    Inventors: Shih-Ching Lin, Chun-Yuan Lai
  • Patent number: 10693490
    Abstract: A Sigma-Delta (?-?) analog-to-digital converter (ADC) and operation method thereof are provided. The ?-? ADC includes a ?-? modulator, a dynamic element matching (DEM) circuit and a control circuit. An input terminal of the ?-? modulator is configured to receive an analog signal. The ?-? modulator is configured to convert the analog signal into a digital signal based on a feedback signal. The DEM circuit is coupled to the ?-? modulator to receive the digital signal. The DEM circuit is configured to perform a DEM algorithm on the digital signal to generate a feedback signal, and provide the feedback signal to the ?-? modulator. The control circuit listens to the digital signal to detect a mute period. The control circuit disables the DEM circuit during the mute period to suspend a progress of the DEM algorithm.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: June 23, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Chiao-Min Chen, Min-Yuan Wu, Shih-Yi Shih, Po-Liang Chen
  • Publication number: 20200162025
    Abstract: An amplifier including a first routing circuit, an input stage circuit, an output stage circuit, a second routing circuit, and a bias voltage generating circuit is provided. The bias voltage generating circuit generates a first bias voltage and a second bias voltage for respectively supplying a first tail current source and a second tail current source of the input stage circuit. During a first period, the first bias voltage is related to the voltage at a first input terminal of the amplifier, and the second bias voltage is related to the voltage at a second input terminal of the amplifier. During a second period, the first bias voltage is related to the voltage at the second input terminal of the amplifier, and the second bias voltage is related to the voltage at the first input terminal of the amplifier.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 21, 2020
    Applicant: Faraday Technology Corp.
    Inventors: Hsu-Ming Tsai, Ta-Wei Wang
  • Patent number: 10644701
    Abstract: An input output circuit and a self-biased circuit are provided. The self-biased circuit includes a tracking circuit, a biasing control circuit and first to fourth transistors. The tracking circuit receives a first power voltage, and generates a bias voltage according to variation of the first power voltage. The biasing control circuit generates a first control signal, a second control signal and a third control signal according to the first power voltage and a voltage on a pad. The first transistor is coupled to the pad and controlled by the first control signal. The second transistor is controlled by the second control signal to provide a bias voltage. The third transistor is coupled to the pad and controlled by the third control signal and generates a fourth control signal according to the voltage on the pad. The fourth transistor is controlled by the fourth control signal to generate the bias voltage.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 5, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Huang-Shiang Su, Chi-Sheng Liao, Jeng-Huang Wu
  • Patent number: 10644706
    Abstract: A data and clock recovery circuit includes a first selecting circuit, a high speed phase detector, a low speed phase detector, a charge pump, a voltage control oscillator and a frequency divider. The high speed phase detector generates a first phase difference signal according to the first reference clock signal and a divided clock signal or according to the data signal and the divided clock signal. The low speed phase detector generates a second phase difference signal according to a second reference clock signal and the divided clock signal. The charge pump generates a control voltage according to the first phase difference signal or the second phase difference signal. The voltage control oscillator receives the control voltage, and generates a recovered clock signal. The frequency divider receives the recovered clock signal, and generates the divided clock signal.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 5, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Young-Bok Kim, Andrew Chao
  • Patent number: 10634706
    Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 28, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Tang-Long Chang, Chi-Sheng Liao, Jeng-Huang Wu
  • Patent number: 10637690
    Abstract: An apparatus for performing decision feedback equalizer (DFE) adaptation control is provided. The apparatus includes arithmetic circuits, slicers, sample and hold circuits, a phase detector and a control circuit for related operations. The control circuit generates parameters at least according to an error sample value and data sample values, and dynamically updates the parameters based on at least one predetermined rule to perform the DFE adaptation control. The parameters include a first parameter, another parameter and a factor adjustment parameter. Regarding at least one data pattern, the control circuit selectively replaces the error sample value with a predetermined value according to whether a temporary storage value of the error sample value conforms to a predetermined condition to control the other parameter and the first parameter, in order to prevent triggering an unstable effect and thereby prevent abnormal operations.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: April 28, 2020
    Assignees: FARADAY TECHNOLOGY CORPORATION, Faraday Technology Corp.
    Inventors: Fu-Chien Tsai, Yin-Fu Lin, Ling Chen
  • Patent number: 10565381
    Abstract: A method and apparatus for performing firmware programming on a microcontroller chip and the associated microcontroller chip are provided.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: February 18, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Chun-Yuan Lai, Chen-Chun Huang
  • Publication number: 20200035670
    Abstract: A electrostatic discharge (ESD) protection apparatus for an integrated circuit (IC) is provided. A first electrostatic current rail and a second electrostatic current rail of the ESD protection apparatus do not directly connected to any bonding pad of the IC. The ESD protection apparatus further includes a clamp circuit and four ESD protection circuits. The clamp circuit is coupled between the first electrostatic current rail and the second electrostatic current rail. A first ESD protection circuit is coupled between the first electrostatic current rail and a signal pad of the IC. A second ESD protection circuit is coupled between the signal pad and the second electrostatic current rail. A third ESD protection circuit is coupled between a first power rail and the second electrostatic current rail. A fourth ESD protection circuit is coupled between the second electrostatic current rail and a second power rail.
    Type: Application
    Filed: October 8, 2018
    Publication date: January 30, 2020
    Applicant: Faraday Technology Corp.
    Inventors: Chia-Ku Tsai, Chi-Sheng Liao, Jeng-Huang Wu
  • Patent number: 10523470
    Abstract: An apparatus for performing baseline wander correction is provided. The apparatus may include: a plurality of filters, a common mode voltage generator, and a compensation circuit. The plurality of filters may filter a set of input signals to generate a set of differential signals, the common mode voltage generator may generate a common mode voltage between the set of differential signals, and the compensation circuit may perform compensation related to baseline wander correction on the set of differential signals. Multiple current paths of the compensation circuit are associated with each other. Through a first current path and a second current path within the current paths, the compensation circuit may perform charge or discharge control on a first capacitor and a second capacitor within the plurality of filters to dynamically adjust compensation amounts of the compensation, to reduce or eliminate a baseline wander effect of the set of differential signals.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 31, 2019
    Assignee: Faraday Technology Corp.
    Inventor: Chia-Lin Hu