Abstract: A memory apparatus includes a memory device, a memory controller and a memory physical layer interface. The memory physical layer interface comprises a multi-tap decision feedback equalization (DFE) receiver and a tap reset circuit. The tap reset circuit generates a pulse signal and a reset signal in accordance with a gap interval between read bursts to reset a DFE taps of the multi-tap DFE receiver during the gap interval between the read bursts. The tap reset circuit resets the plurality of DFE taps using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval. The tap reset circuit resets the plurality of DFE taps of the multi-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval. The second predetermined interval is greater than the first predetermined interval.

Abstract: An output buffer includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a control circuit, and a tracking circuit. The second P-type transistor and the first P-type transistor are coupled between a supply voltage and a pad, and the second N-type transistor and the first N-type transistor are coupled between a ground voltage and the pad. The control circuit is arranged to generate two first gate control signals according to a control signal for controlling the first P-type transistor and the first N-type transistor. The tracking circuit is coupled to the pad, and is arranged to generate a second gate control signal according to the output signal for controlling the second P-type transistor or the second N-type transistor.

Abstract: A method for performing bus instance (BI) resource management in a USB host controller and associated apparatus are provided. The method applicable to the USB host controller includes: establishing a BI bandwidth table for recoding respective bandwidth usage information of multiple BIs of the USB host controller; utilizing a scheduler within the USB host controller to determine whether a predetermined command is received; utilizing the scheduler to determine whether the predetermined command indicates that any endpoint is added; utilizing a resource calculator within the USB host controller to perform a lookup operation on the BI bandwidth table, for determining whether a target bandwidth of a target BI among the multiple BIs exceeds a predetermined bandwidth limit per BI; and utilizing the resource calculator to perform at least one searching operation for collecting at least one remaining bandwidth of at least one other BI for being used by the target BI.

Abstract: The present invention provides a circuit including a logic circuit and a power switch module. The power switch module includes multiple switches, a voltage detection circuit and a control circuit. Each switch includes a control node, a first node and a second node, the first node is coupled to a supply voltage, the second node is coupled to the logic circuit; and the multiple switches comprise a first switch and multiple second switches, and the control node of the first switch receives a power enable signal. The voltage detection circuit is configured to detect whether a voltage of the second node of the first switch is greater than a reference voltage to generate a detection result. The control circuit is configured to generate an output power enable signal to the multiple second switches according to the detection result.

Abstract: The disclosure provides an evaluation circuit for SRAM operations. The evaluation circuit includes a ring-oscillation control circuit and a plurality of SRAM instances connected in series with each other into an SRAM string. A WLE signal input terminal of an intermediate SRAM instance in the SRAM string is coupled to an internal signal output terminal of a previous-stage SRAM instance, and an internal signal output terminal of the intermediate SRAM instance is coupled to a WLE signal input terminal of a next-stage SRAM instance. An input terminal of the ring-oscillation control circuit is coupled to an internal signal output terminal of a last-stage SRAM instance in the SRAM string, and an output terminal of the ring-oscillation control circuit is coupled to a WLE signal input terminal of a first-stage SRAM instance in the SRAM string. Therefore, the ring-oscillation control circuit and the SRAM string form a ring oscillator circuit.

Abstract: An output buffer includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a control circuit, and a tracking circuit. The second P-type transistor and the first P-type transistor are coupled between a supply voltage and a pad, and the second N-type transistor and the first N-type transistor are coupled between a ground voltage and the pad. The control circuit is arranged to generate two first gate control signals according to a control signal for controlling the first P-type transistor and the first N-type transistor. The tracking circuit is coupled to the pad, and is arranged to generate a second gate control signal according to the output signal for controlling the second P-type transistor or the second N-type transistor.

Abstract: A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

Abstract: A bandgap device and a start-up circuit thereof are disclosed. The start-up circuit includes a first transistor, delay circuit, second transistor, switch circuit, and startup switch. Control terminals of first transistor and second transistor are controlled by an internal bias voltage of the bandgap circuit. The delay circuit is coupled to the first transistor. The switch circuit is coupled to the second transistor. The switch circuit is controlled by the delay circuit. A control terminal of startup switch is coupled to the second transistor and the switch circuit. At a power-up instant time of the bandgap circuit, the startup switch is turned on to provide a startup bias to an internal startup node of the bandgap circuit. After the bandgap circuit completes startup, the internal bias voltage of the bandgap circuit turns off the startup switch, the first transistor, and the second transistor, so the start-up circuit consumes no current.

Abstract: A method and apparatus for performing self-calibration of receiver offset without shorting differential input terminals of a receiver are provided. The self-calibration includes: inputting input signals carrying predetermined data patterns into a plurality of receivers; performing data eye width measurement on the input signals received by the plurality of receivers to obtain multiple first data eye widths and multiple second data eye widths respectively corresponding to first and second data bytes; performing first offset calibration to make the multiple first data eye widths converge to a first common data eye width; performing second offset calibration to make the multiple second data eye widths be equal to the multiple first data eye widths, respectively, and converge to the first common data eye width; and performing reference voltage calibration on a reference voltage to optimize the multiple first data eye widths and the multiple second data eye widths.

Abstract: The present invention provides a circuit including a logic circuit and a power switch module. The power switch module includes multiple switches, a voltage detection circuit and a control circuit. Each switch includes a control node, a first node and a second node, the first node is coupled to a supply voltage, the second node is coupled to the logic circuit; and the multiple switches comprise a first switch and multiple second switches, and the control node of the first switch receives a power enable signal. The voltage detection circuit is configured to detect whether a voltage of the second node of the first switch is greater than a reference voltage to generate a detection result. The control circuit is configured to generate an output power enable signal to the multiple second switches according to the detection result.

Abstract: A voltage regulator provides a regulated voltage to a double data rate (DDR) Physical Interface (PHY) including a plurality of delay elements. The voltage regulator includes: an amplifier, for receiving a voltage at a first input terminal and generating an output voltage; a first MOSFET coupled to a supply voltage and a second input terminal of the amplifier; a second MOSFET coupled in parallel with the first MOSFET for generating a first current in response to a first enable signal; a load, coupled to the first MOSFET and the second MOSFET, for generating the regulated voltage; and a load capacitor, coupled in parallel with the load. The first enable signal is generated by inputting a gate enable signal for a delay element of the plurality of delay elements into a delay circuit corresponding to the delay element.

Abstract: The disclosure provides an electronic fuse (eFuse) device and an operation method thereof. The eFuse device includes an eFuse, a readout circuit, a register, and a safety control device. The readout circuit reads out target data recorded by the eFuse to the register and the safety control device. The safety control device compares the target data provided by the readout circuit with the target data provided by the register to determine whether a soft error occurs in the target data stored in the register. When the soft error occurs in the target data stored in the register, the readout circuit reads out the target data recorded by the eFuse again to the register and the safety control device.

Abstract: The present invention discloses a regulator. The regulator includes a bias voltage generating circuit and a flipped voltage follower (FVF), wherein the bias voltage generating circuit is configured to generate a bias voltage, and the FVF is configured to generate an output voltage according to the bias voltage and a supply voltage. The FVF includes a first P-type transistor and a first N-type transistor. The P-type transistor is configured to receive the bias voltage via a gate electrode of the P-type transistor, to generate the output voltage on a source electrode of the P-type transistor. A drain electrode of the first N-type transistor is connected to the supply voltage, a source electrode of the first N-type transistor is connected to the source electrode of the first P-type transistor, and a gate electrode of the first N-type transistor receives a driving signal for compensating the output voltage.

Abstract: A command reorder device with a retry function and an operation method thereof are provided. The command reorder device includes a first switch circuit, multiple command buffers, a second switch circuit, and a queue control circuit. The queue control circuit controls the first switch circuit to push an input command of an input command string to a first command buffer. The queue control circuit controls the second switch circuit to pop out an output command from a second command buffer based on a programmable reorder policy. The queue control circuit checks whether an error notification is received during a monitoring period from when the output command is popped out from the second command buffer. According to the check result, the queue control circuit determines either to pop out the output command from the second command buffer again, or to release the memory space of the second command buffer.

Abstract: A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.

Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.

Abstract: A content addressable memory (CAM) and a CAM cell are provided. The CAM includes a memory cell array and a disabling circuit. The memory cell array includes a plurality of CAM cells, wherein each of the CAM cells includes a memory cell circuit and a comparison circuit. When the CAM cells in a first column of the memory cell array are normal, the disabling circuit enables the comparison circuits of the CAM cells in the first column, so that the comparison circuits in the first column respectively present the comparison results on different match lines. When any one of the CAM cells in the first column is defective, the disabling circuit disables the comparison circuits of the CAM cells in the first column, so that the disabled comparison circuits does not affect the different match lines.

Abstract: A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.

Abstract: The disclosure provides an electronic fuse (eFuse) device and an operation method thereof. The eFuse device includes an eFuse, a readout circuit, a register, and a safety control device. The readout circuit reads out target data recorded by the eFuse to the register and the safety control device. The safety control device compares the target data provided by the readout circuit with the target data provided by the register to determine whether a soft error occurs in the target data stored in the register. When the soft error occurs in the target data stored in the register, the readout circuit reads out the target data recorded by the eFuse again to the register and the safety control device.