Abstract: An input output circuit and a self-biased circuit are provided. The self-biased circuit includes a tracking circuit, a biasing control circuit and first to fourth transistors. The tracking circuit receives a first power voltage, and generates a bias voltage according to variation of the first power voltage. The biasing control circuit generates a first control signal, a second control signal and a third control signal according to the first power voltage and a voltage on a pad. The first transistor is coupled to the pad and controlled by the first control signal. The second transistor is controlled by the second control signal to provide a bias voltage. The third transistor is coupled to the pad and controlled by the third control signal and generates a fourth control signal according to the voltage on the pad. The fourth transistor is controlled by the fourth control signal to generate the bias voltage.

Abstract: An apparatus for performing decision feedback equalizer (DFE) adaptation control is provided. The apparatus includes arithmetic circuits, slicers, sample and hold circuits, a phase detector and a control circuit for related operations. The control circuit generates parameters at least according to an error sample value and data sample values, and dynamically updates the parameters based on at least one predetermined rule to perform the DFE adaptation control. The parameters include a first parameter, another parameter and a factor adjustment parameter. Regarding at least one data pattern, the control circuit selectively replaces the error sample value with a predetermined value according to whether a temporary storage value of the error sample value conforms to a predetermined condition to control the other parameter and the first parameter, in order to prevent triggering an unstable effect and thereby prevent abnormal operations.

Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.

Abstract: A method and apparatus for performing firmware programming on a microcontroller chip and the associated microcontroller chip are provided.

Abstract: A electrostatic discharge (ESD) protection apparatus for an integrated circuit (IC) is provided. A first electrostatic current rail and a second electrostatic current rail of the ESD protection apparatus do not directly connected to any bonding pad of the IC. The ESD protection apparatus further includes a clamp circuit and four ESD protection circuits. The clamp circuit is coupled between the first electrostatic current rail and the second electrostatic current rail. A first ESD protection circuit is coupled between the first electrostatic current rail and a signal pad of the IC. A second ESD protection circuit is coupled between the signal pad and the second electrostatic current rail. A third ESD protection circuit is coupled between a first power rail and the second electrostatic current rail. A fourth ESD protection circuit is coupled between the second electrostatic current rail and a second power rail.

Abstract: An apparatus for performing baseline wander correction is provided. The apparatus may include: a plurality of filters, a common mode voltage generator, and a compensation circuit. The plurality of filters may filter a set of input signals to generate a set of differential signals, the common mode voltage generator may generate a common mode voltage between the set of differential signals, and the compensation circuit may perform compensation related to baseline wander correction on the set of differential signals. Multiple current paths of the compensation circuit are associated with each other. Through a first current path and a second current path within the current paths, the compensation circuit may perform charge or discharge control on a first capacitor and a second capacitor within the plurality of filters to dynamically adjust compensation amounts of the compensation, to reduce or eliminate a baseline wander effect of the set of differential signals.

Abstract: An electrostatic discharge (ESD) protection apparatus includes: an ESD circuit, arranged to perform ESD protection, wherein the ESD circuit includes a first Field Effect Transistor (FET) arranged to release ESD energy; a detection circuit, arranged to perform detection to control the ESD protection apparatus to selectively operate in one of a normal mode and a discharge mode; and a logic circuit, arranged to withstand any oscillation due to resistance-inductance-capacitance (RLC) characteristics of the detection circuit. In the detection circuit, different subsets of a plurality of resistors are respectively combined with a portion of a first serial connection circuit, an entirety of the first serial connection circuit, and a second FET to form different serial connection circuits, to configure the second FET to approach a state of being completely turned off in the normal mode.

Abstract: A power distribution network adapted to provide power to a plurality of components in an integrated circuit is provided. The power distribution network includes a power distribution trunk path, a plurality of first power distribution branch paths, and a plurality of second power distribution branch paths. The power distribution trunk path is used for transmitting the power. A long axis direction of the power distribution trunk path is a first direction. The first power distribution branch paths and the second power distribution branch paths are electrically connected to the power distribution trunk path. A long axis direction of the first power distribution branch paths is a second direction different from the first direction. A long axis direction of the second power distribution branch paths is a third direction different from the first direction and the second direction.

Abstract: In a voltage generating circuit, a bandgap voltage generator has a first operational amplifier to receive a first voltage and a second voltage, and generate a bias voltage by comparing the first voltage and the second voltage, wherein the bandgap voltage generator generates a bandgap current according to the bias voltage and generates an output voltage according to the bandgap current. In a start-up circuit, a comparison circuit compares the first voltage or the second voltage with a reference voltage to generate a first comparison result, and generates a first current according to the first comparison result. A voltage regulator generates a second current according to the first current, and compares the second current with a reference current to generate a second comparison result, and adjusts a voltage value of the bias voltage according to the second comparison result.

Abstract: In a voltage generating circuit, a bandgap voltage generator has a first operational amplifier to receive a first voltage and a second voltage, and generate a bias voltage by comparing the first voltage and the second voltage, wherein the bandgap voltage generator generates a bandgap current according to the bias voltage and generates an output voltage according to the bandgap current. In a start-up circuit, a comparison circuit compares the first voltage or the second voltage with a reference voltage to generate a first comparison result, and generates a first current according to the first comparison result. A voltage regulator generates a second current according to the first current, and compares the second current with a reference current to generate a second comparison result, and adjusts a voltage value of the bias voltage according to the second comparison result.

Abstract: A FIFO circuit for a DDR memory system includes a pointer generator and a FIFO circuit. The FIFO circuit includes a pointer generator and a FIFO buffer. The pointer generator receives a first reset signal and a delay select signal from the memory controller. After the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock. An input data is stored into the FIFO buffer according to the first reference clock and the write pointer. An output data is outputted from the FIFO buffer according to the second reference clock and the read pointer.

Abstract: A receiver and a common-mode voltage calibration method thereof are provided. The receiver includes sensing circuits, a phase comparator, and a self-calibration circuit. The phase comparator compares phase relationships of the latch results at the output terminals of the sensing circuits during a testing period to produce a phase comparison result. During the testing period, the self-calibration circuit provides the same differential signal to the input terminals of these sensing circuits, and sets common-mode levels at the input terminals of these sensing circuits to be different from one another. The self-calibration circuit determines a calibrated common-mode level based on the phase comparison result. The self-calibration circuit sets the common-mode levels at the input terminals of these sensing circuits to be equal to the calibrated common-mode level during a normal operation period.

Abstract: A power distribution network adapted to provide power to a plurality of components in an integrated circuit is provided. The power distribution network includes a power distribution trunk path, a plurality of first power distribution branch paths, and a plurality of second power distribution branch paths. The power distribution trunk path is used for transmitting the power. A long axis direction of the power distribution trunk path is a first direction. The first power distribution branch paths and the second power distribution branch paths are electrically connected to the power distribution trunk path. A long axis direction of the first power distribution branch paths is a second direction different from the first direction. A long axis direction of the second power distribution branch paths is a third direction different from the first direction and the second direction.

Abstract: The disclosure provides a voltage generating device and a calibrating method thereof. The voltage generating device includes a bandgap circuit, a regulator circuit and a calibrating circuit. The bandgap circuit provides a bandgap voltage. The regulator circuit generates an output voltage correspondingly according to the bandgap voltage. In a first stage of a calibration period, the calibrating circuit detects the bandgap voltage, and correspondingly sets a resistance of at least one resistor of the bandgap circuit according to the bandgap voltage. In a second stage of the calibration period, the calibrating circuit detects the output voltage, and correspondingly sets a resistance of at least one resistor of the regulator circuit according to the output voltage.

Abstract: An analog-to-digital conversion device is provided for converting an input signal pair to generate an output signal. The analog-to-digital conversion device includes switch groups, capacitors, a comparator, and a controller. The switch groups receive the input signal pair and reference voltages, and selects to output one of the input signal pair and the reference voltages according to a control signal to generate selection voltages respectively. The capacitors receive the selection voltages respectively and generate a first comparison voltage and a second comparison voltage. The comparator compares the first comparison voltage and the second comparison voltage to generate a comparison result signal. The controller sets conversion times for converting bits of the output signal according to the comparison result signal, wherein at least two of the conversion times are different.

Abstract: An arbitrating circuit includes a first NOR gate, a second NOR gate, four resistors and a pull-up circuit. The first transistor is connected with the first node and the second node, and generates a first acknowledging signal. The second transistor is connected with a supply voltage, the second node and the first transistor. The third transistor is connected with the first node and second node, and generates a second acknowledging signal. The fourth transistor is connected with the supply voltage, the first node and the third transistor. The pull-up circuit is connected with the first node, the second node, the first NOR gate and the second NOR gate. If both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.

Abstract: An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.

Abstract: A voltage regulator is connected with an input/output circuit. The voltage regulator includes a controlling circuit, a sink voltage generator and a source voltage generator. The controlling circuit generates a first reference voltage, a second reference voltage, a first power start control signal and a second power start control signal. The sink voltage generator receives the first reference voltage and the first power start control signal. The source voltage generator receives the second reference voltage and the second power start control signal. When the voltage regulator is in a normal working state, the controlling circuit inactivates the first power start control signal and the second power start control signal, the sink voltage generator generates a sink voltage according to the first reference voltage, and the source voltage generator generates a source voltage according to the second reference voltage.

Abstract: An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration preparation state and a signal of a first calibration input pin is an enable state, or when the SERDES PHY layer circuit is in the calibration preparation state, and signals of first and second calibration input pins are in the enable state, the SERDES PHY layer circuit enters a calibration state (using a reference resistor for current calibration). After the current calibration is completed, the SERDES PHY layer circuit enters a calibration completion state (without using the reference resistor and connecting the first calibration input pin to the first calibration output pin). The SERDES PHY layer circuit sets the signal of the first calibration output pin to a disable state when the SERDES PHY layer circuit is not in the calibration completion state.

Abstract: An amplifier with adjustable gain including a plurality of differential amplifiers and an output stage circuit is provided. Each of the differential amplifiers has at least one differential pair, two current terminals of each of the differential pairs are coupled by a connection structure, and the connection structure provides a negative feedback resistance. The differential amplifiers commonly receive a differential input signal pair, and output terminals of the differential amplifiers are coupled together. The output stage circuit inverts a voltage on the output terminals of the differential amplifiers to generate an output voltage. A direct current gain of the amplifier with adjustable gain is determined by adjusting at least one of working numbers of the differential amplifiers and the differential pairs.