Abstract: A Double Data Rate (DDR) gating method is applied to a memory controller of an associated DDR gating apparatus. The DDR gating method includes: outputting from the memory controller an outward clock signal to a memory, and receiving from the memory a backward clock signal corresponding to the outward clock signal, wherein the backward clock signal is utilized as reference for a data read operation of the memory controller with respect to the memory; and providing an input stage of the memory controller with a reference signal to generate, through single ended receiving of the input stage, gating-related information for performing gating when sampling the backward clock signal, and lengthening time of a preamble of the backward clock signal with aid of the single ended receiving of the input stage, for increasing a detection margin of the preamble.

Abstract: An amplifier with adjustable gain including a plurality of differential amplifiers and an output stage circuit is provided. Each of the differential amplifiers has at least one differential pair, two current terminals of each of the differential pairs are coupled by a connection structure, and the connection structure provides a negative feedback resistance. The differential amplifiers commonly receive a differential input signal pair, and output terminals of the differential amplifiers are coupled together. The output stage circuit inverts a voltage on the output terminals of the differential amplifiers to generate an output voltage. A direct current gain of the amplifier with adjustable gain is determined by adjusting at least one of working numbers of the differential amplifiers and the differential pairs.

Abstract: An apparatus and a method for video frame rotation are provided. The apparatus includes a synchronous dynamic random access memory (SDRAM) and a video rotation circuit. The video rotation circuit is coupled to the SDRAM. The video rotation circuit sequentially writes a plurality of pixels of a video frame into the SDRAM in a row-by-row scanning manner. The video rotation circuit divides a plurality of columns of the video frame into a plurality of column sets, so as to divide each of the rows of the video frame into a plurality of sub-rows. The video rotation circuit performs an internal column-set scanning for each of the column sets in a column-set-by-column-set manner, so as to discretely read the sub-rows from the SDRAM.

Abstract: A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.

Abstract: A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit, a cache unit, and an access interface circuit. The data pre-fetching unit has a plurality of line buffers. One of the line buffers provides read data according to a read command, or the data pre-fetching unit reads at least one cache data as the read data according to the read command. The data pre-fetching unit further stores in at least one of the line buffers a plurality of pre-stored data with continuous addresses according to the read command. The cache unit stores the at least one cache data and the pre-stored data with the continuous addresses. The access interface circuit is configured to be an interface circuit of the non-volatile memory.

Abstract: A power system includes a voltage regulating system and a digital circuit. The voltage regulating system receives a power down signal. The voltage regulating system selectively generates an output voltage according to the power down signal. When the digital circuit receives the output voltage, the digital circuit is operated. When the digital circuit is not operated, the power down signal is activated. After the external voltage source is switched on and before a voltage of the external voltage source reaches a fixed voltage, the voltage regulating system ignores the power down signal and generates the output voltage. After the voltage of the external voltage source reaches the fixed voltage, the voltage regulating system generates the output voltage if the power down signal is inactivated; the voltage regulating system stops generating the output voltage if the power down signal is activated.

Abstract: A power-on-reset circuit including a first diode-connected transistor, a second diode-connected transistor, a resistor and a current comparator circuit is provided. A cathode of the first diode-connected transistor is coupled to a reference voltage. A first end of the resistor is coupled to a power voltage. A second end of the resistor is coupled to an anode of the first diode-connected transistor. A cathode of the second diode-connected transistor is coupled to the reference voltage. An anode of the second diode-connected transistor is coupled to the first end of the resistor. The current comparator circuit is coupled to the first diode-connected transistor and the second diode-connected transistor. The current comparator circuit compares a current of the first diode-connected transistor with a current of the second diode-connected transistor to obtain a comparing result, wherein the comparing result determines a reset signal.

Abstract: A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.

Abstract: A crystal oscillation circuit, a gain stage of the crystal oscillation circuit and a method for designing the same are provided. The gain stage includes multiple amplifiers and multiple current-limiting resistors. Input terminals of the amplifiers are coupled together to a first bonding pad, wherein transconductances of the amplifiers are different from each other. The first bonding pad is used for electrically coupling to a first terminal of an oscillation crystal module. First terminals of the current-limiting resistors are respectively coupled to output terminals of the amplifiers in a one-on-one manner, and second terminals of the current-limiting resistors are coupled together to a second bonding pad, wherein the second bonding pad is used for electrically coupling to a second terminal of the oscillation crystal module.

Abstract: A crystal oscillation circuit, a gain stage of the crystal oscillation circuit and a method for designing the same are provided. The gain stage includes multiple amplifiers and multiple current-limiting resistors. Input terminals of the amplifiers are coupled together to a first bonding pad, wherein transconductances of the amplifiers are different from each other. The first bonding pad is used for electrically coupling to a first terminal of an oscillation crystal module. First terminals of the current-limiting resistors are respectively coupled to output terminals of the amplifiers in a one-on-one manner, and second terminals of the current-limiting resistors are coupled together to a second bonding pad, wherein the second bonding pad is used for electrically coupling to a second terminal of the oscillation crystal module.

Abstract: A driving circuit used in a transmission line includes an operational amplifier and an output circuit. The operational amplifier is used for receiving a voltage signal to generate an output. The output circuit is coupled to the operational amplifier and used for receiving the output of the operational amplifier and determining current(s) passing through the output circuit to generate an output signal of the driving signal so as to adjust the output impedance of the driving circuit to match the transmission line; the output impedance of driving circuit is adjustable and determined by the current(s) passing through the output circuit.

Abstract: A method and an apparatus for signal extraction of audio signal are provided. An audio signal is converted into a plurality of frames, and the frames are arranged in a chronological order. Spectral data of each of the frames is obtained. The spectral data of each of N frames is extracted in the chronological order, and a spectral connectivity operation is executed for the N frames. Finally, the signal including the frames having the spectral connectivity between adjacent frames in each of the frames is determined as an ideal signal.

Abstract: A static memory apparatus and a static memory cell thereof are provided. The static memory cell includes a data latch circuit, a data write-in circuit and a data read-out circuit. The data latch circuit has a first tristate output inverting circuit and a second tristate output inverting circuit. The data write-in circuit provides a first reference voltage to a power receiving terminal of a selected tristate output inverting circuit which is one of the first and second tristate output inverting circuits, and provides a second reference voltage to an input terminal of the selected tristate output inverting circuit during a data write-in time period. The data read-out circuit generates read-out data according to a voltage at an output terminal of the second tristate output inverting circuit and the second reference voltage during a data read-out time period.

Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.

Abstract: An integrated circuit (IC) including a unit area, a first input/output (IO) cell, a second IO cell, an electrostatic discharge (ESD) component, a first IO pad and a second IO pad is provided. The unit area is divided into several subareas, wherein a subarea of an ith column and a jth row of those subareas is defined as SA(i,j). The first IO cell is arranged in subareas SA(i,j) and SA(i,j+1) of those subareas. The second IO cell is arranged in a subarea SA(i+1,j+1) of those subareas. The ESD component is arranged in at lease one of the subareas of the jth row. The first IO pad is arranged on the first IO cell, and electrically connected to the first IO cell. The second IO pad is arranged on the second IO cell, and electrically connected to the second IO cell.

Abstract: A voltage regulator includes an operational amplifier, a transistor, a first resistor, a second resistor, an output voltage delaying circuit and a selecting circuit. The output voltage delaying circuit receives an output voltage and generates a delayed output voltage. A first input terminal of the selecting circuit receives a reference voltage. A second input terminal of the selecting circuit receives the delayed output voltage. An output terminal of the selecting circuit generates a control voltage to a first input terminal of the operational amplifier. If the reference voltage is larger than the delayed output voltage, the selecting circuit selects the delayed output voltage as the control voltage. If the reference voltage is smaller than the delayed output voltage, the selecting circuit selects the reference voltage as the control voltage.

Abstract: A method and an apparatus for detecting noise of audio signals are provided. The method includes steps of converting an audio signal into a plurality of audio frames, where the audio frames are arranged in chronological order while taking a target frame as a center, calculating a plurality of magnitudes respectively corresponding to a plurality of spectral components of each of the audio frames, calculating differences between the adjacent magnitudes in a time-frequency domain to obtain a plurality of difference values in at least two directions orthogonal to each other in the time-frequency domain, where the time-frequency domain is defined by the audio frames, determining a maximum degree of difference of the magnitudes in the time-frequency domain according to the difference values, and determining whether a part of the audio signal corresponding to the target frame is a noise according to the maximum degree of difference.

Abstract: A successive approximation analog-to-digital converter includes a first capacitance bank, a second capacitance bank, a bridge capacitor, a switch set, a comparator and a successive approximation register logic circuit. The first capacitance bank is connected with a first node. The second capacitance bank is connected with a second node. The bridge capacitor is connected between the first node and the second node. Two first input terminals of the comparator are connected with the first node and the intermediate level, respectively. An output terminal of the comparator generates a comparing signal. The successive approximation register logic circuit receives the comparing signal, and generates the switching signal and a digital data signal. The switch set selectively provides one of a low reference level, a high reference level, an input level and an intermediate level to the first capacitance bank and the second capacitance bank.

Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Abstract: A method and apparatus for performing de-skew control are provided, where the method is applied to an electronic device. The method includes the steps of: performing a symbol detection at a plurality of lanes of the electronic device, respectively, to determine locations of a specific symbol at the plurality of lanes, respectively; according to the locations of the specific symbol at the plurality of lanes, selectively rearranging decoded data in the plurality of lanes to generate a plurality of sets of de-skewed data respectively corresponding to the plurality of lanes; and by buffering the plurality of sets of de-skewed data, selectively delaying output of the plurality of sets of de-skewed data to control beginning of the plurality of sets of de-skewed data to be simultaneously output.