Abstract: An SoC architecture includes a non-volatile memory and an SoC chip. The SoC chip is connected with the non-volatile memory. The SoC chip includes a central processing unit, a volatile memory, a system bus, an on-the-fly decryption circuit, a memory interface, a timer and a key bank. The on-the-fly decryption circuit is connected with the key bank. The on-the-fly decryption circuit performs an encryption operation or a decryption operation according to plural keys in the key bank. After the SoC architecture is powered on, if the timer is not disabled and the timer has counted time for a specified time period, the central processing unit is subjected to a warm reset, and a storage format in the non-volatile memory is changed from an initial format to an operation format by the central processing unit.

Abstract: A serial signal detector and a differential signal detection method are provided. The serial signal detector includes a voltage comparison module and a hybrid logic filter. The voltage comparison module receives a differential signal, including a first shifted signal and a second shifted signal. The voltage comparison module includes a first comparator and a second comparator. Based on the first shifted signal, the second shifted signal, and a voltage threshold, the first and the second comparators respectively generate a first and a second comparison signals. The hybrid logic filter includes a controllable logic gate and a capacitor. The controllable logic gate performs a logic operation related to the first and the second comparison signals and generates a filtered and converted pulse accordingly. The controllable logic gate and the capacitor jointly perform a preliminary filtering operation to the filtered and converted pulse while the logic operation is being performed.

Abstract: A power mesh structure for an integrated circuit is provided. A power switch cell is installed on the chip of the integrated circuit to control the switching operations of the power domain. The power meshes of the power mesh structure is specially designed. The power wires with different electrical properties are arranged in the same column or the same row to reduce the layout area of the power mesh on the material layer.

Abstract: A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.

Abstract: The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.

Abstract: A de-skew circuit, a de-skew method and a receiver are provided. The de-skew circuit includes N data synchronization circuits and a controller. An nth data synchronization circuit among the N data synchronization circuits includes an nth command detector and an nth buffer. The nth command detector changes an nth command detection signal when an nth input data stream satisfies a single channel condition. The nth buffer stores the nth input data stream in response to a voltage change of the nth command detection signal. The controller receives the nth command detection signal and changes a pop signal when a global channel condition is satisfied. The nth buffer outputs an nth timing-aligned data stream in response to a voltage change of the pop signal.

Abstract: A receiver device and an eye pattern-based control parameter adjustment method are provided. The receiver device includes a receiving circuit and a control circuit. The control circuit performs an iterative operation to determine an optimized control parameter, and updates current control parameters of the receiving circuit to the optimized control parameter after completing the iterative operation. The receiving circuit processes an input signal according to the current control parameters to generate recovered data. The iterative operation includes: updating the current control parameters of the receiving circuit to candidate control parameters; checking a size relationship between an optimized eye mask and a current eye pattern; and increasing the optimized eye mask according to the current eye pattern when the optimized eye mask does not conflict with the current eye pattern, and updating the optimized control parameters to the candidate control parameters corresponding to the new eye mask.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: An input/output module electrically coupled between a control circuit and an input/output pin is provided. The input/output module includes a pre-driver and a post-driver. The pre-driver is electrically coupled to the control circuit, and the post-driver is electrically coupled between the pre-driver and the input/output pin. The pre-driver generates a pull-up selection signal and a pull-down selection signal according to an input signal and an enable signal generated by the control circuit. The post-driver sets a voltage level of the input/output pin according to the pull-up and pull-down selection signals. When the enable signal is at a first logic level, the input/output pin has a high impedance. When the enable signal is at a second logic level, the voltage level of the input/output pin changes with a logic level of the input signal, wherein the first logic level and the second logic level are inverted.

Abstract: The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: An analog-to-digital converter (ADC) device equipped with a conversion suspension function and an associated operation method thereof are provided. The ADC device includes: an interleaved clock controller, arranged to generate a first clock signal and a second clock signal according to a master clock signal; and a multi-ADC circuit, coupled to the interleaved clock controller, arranged to perform analog-to-digital conversion. The multi-ADC circuit includes a first ADC and a second ADC, wherein the first ADC performs sampling and conversion operations according to the first clock signal, and the second ADC performs sampling and conversion operations according to the second clock signal. Based on the timing control of the first clock signal and the second clock signal, when any ADC of the first ADC and the second ADC is performing a sampling operation, the other ADC of the first ADC and the second ADC suspends conversion.

Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.

Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

Abstract: A method for controlling a multi-cycle write leveling process in a memory system is provided. After a write leveling process is completed and before a write training process is performed, the multi-cycle write leveling process is performed. Consequently, when a DDR memory of the memory system receives a clock signal and a first data strobe signal, the DDR memory can confirm that the signal edges of the clock signal and the first data strobe signal are aligned with each other and the signal edges are accurate.

Abstract: A dynamic module and a decision feedback equalizer are provided. The decision feedback equalizer includes two dynamic modules, which have symmetric circuits and connections. The dynamic module includes a first domino circuit, a second domino circuit, and a storage circuit. In response to a first previous decision bit and a second previous decision bit, a first multiplexer output and a second multiplexer output are generated. The dynamic module alternatively operates in an evaluation period and a precharge period, depending on a clock signal. In the evaluation period, the first and the second multiplexer outputs are updated by the first domino circuit and the second domino circuit. In the precharge period, the first and the second multiplexer outputs are held by the storage circuit.

Abstract: A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.

Abstract: A comparing circuit and a comparing module with hysteresis are provided. The comparing module includes a first resistor, a second resistor, and the comparing circuit, which are electrically connected to each other. A comparison voltage is determined according to an input voltage and the resistances of the first resistor and the second resistor. The comparing circuit includes an input circuit, an eternal circuit, and a coupling module. The coupling module includes a first coupling transistor, a second coupling transistor, a third transistor, and a fourth coupling resistor. Control terminals of the first coupling transistor and the second coupling transistor are selectively electrically connected to either one of a first terminal and a second terminal. The second terminals of the third coupling transistor and the fourth coupling transistor are selectively electrically connected to either one of the first terminal and the second terminal.