Abstract: Field color sequential (FCS) imaging method and technology/apparatus based on FCS principle are provided. In an embodiment, while displaying a frame based on FCS principle, the invention includes: extracting at least a monochrome subfield value and at least a mixed subfield value from each color channel of each pixel of the frame, writing corresponding monochrome subfield value of each pixel in association with a single color channel, and writing corresponding mixed subfield value of each pixel in association with a mixed color which is mixed by at least two color channels.

Abstract: An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.

Abstract: A small area IO circuit is provided. The IO circuit has one or more parallel circuit unit(s) and an ESD protector set between a core circuit/pre-driver and an IO pad. Each circuit unit includes an off-chip driver and an output resistor, wherein the ESD protector protects ESD event occurred at the IO pad, and the resistor in each circuit unit acts as an ESD block circuit to block ESD current from corresponding off-chip driver. Therefore, transistors in each off-chip driver do not have to be restricted by strict ESD design rules, such that at least a transistor of the off-chip driver(s) is implemented in a single finger layout to lower equivalent capacitance of the off-chip driver(s), and layout areas of the off-chip driver(s) as well as the whole IO circuit can be reduced to achieve a small area IO circuit.

Abstract: Method and apparatus of testing die to die interconnection for system in package (SiP). For testing a die to die interconnection connected between two pads of two dice, an IO buffer, e.g., a bi-directional IO buffer, in one of the two dice coupled to one of the two pads is arranged. An oscillating feedback is formed between an output port and an input port of the IO buffer, such that a state, e.g., an open state, a short state or a normal state of the die to die interconnection is tested according to a timing characteristic, e.g., a frequency, of a signal of the IO buffer.

Abstract: A reference circuit for providing a precision voltage and a precision current includes a bandgap voltage reference circuit, a positive temperature coefficient calibrating circuit, a threshold voltage superposing circuit and precision current generator interconnected in cascade. From the bandgap voltage reference circuit, a bandgap voltage is outputted as the precision voltage, and a PTAT current is outputted to the positive temperature coefficient calibrating circuit along with the bandgap voltage for generating a PTAT voltage. In response to the PTAT voltage from the positive temperature coefficient calibrating circuit, the threshold voltage superposing circuit generates a first voltage which is equal to the PTAT voltage plus a threshold voltage. Then the precision current generator outputs a reference current as the precision current in response to the first voltage.

Abstract: Method and technique for analogue circuit synthesis. An analogue circuit usually includes many circuit components, and characteristics and functions of each circuit component are controlled by many corresponding parameters. In the presented invention, selected key design parameters of selected critical circuit components, as well as optimization targets, design specification or/and design constraint, are transformed into an optimization plan, and an optimization engine iterates circuit level or system level numerical simulations by changing values of the selected key design parameters recorded in the optimization plan, so as to find optimized parameters and circuit components which allow the analogue circuit to match the design specification/constraint and to approach the optimization target. Thus a systematic automation for analogue circuit synthesis/design/optimization is achieved.

Abstract: An isolation cell having a test mode, connected between a first block and a second block, wherein the first block can operate in either a power-up mode or a power-down mode, comprises: an input terminal for receiving an input signal that is derived from the first block; an output terminal for outputting an output signal to the second block; a normal-sleep terminal for determining the isolation cell is operated in the power-up mode or in the power-down mode, and the logic level of the normal-sleep terminal is determined by the operation mode of the first block; and, a DFT-sleep terminal is for overwriting the logic level of the normal-sleep terminal when the isolation cell is in the test mode.

Abstract: A spread spectrum clock generator includes: a phase frequency detector, for generating a phase difference signal according to a frequency divided signal and a reference signal with a reference frequency; a charge pump, for receiving the phase difference signal and generating an output current according to the phase difference signal; a loop filter, for receiving the output current and converting the output current to a voltage-controlled signal; a voltage-controlled oscillator, for receiving the voltage-controlled signal and generating a plurality of voltage-controlled output signals, wherein the plurality of voltage-controlled signals have a specific phase difference and a same voltage-controlled frequency; a frequency dividing unit, for receiving the plurality of voltage-controlled output signal and generating the frequency divided signal; and a delta-sigma modulator, for controlling the frequency dividing unit to have an equivalent divided value of (N+b)S+(N?a)(P?S) through receiving the frequency divided

Abstract: A differential to single ended converting circuit includes a transconductance circuit having input terminals for receiving differential input voltages and having a first current output terminal for outputting a first current and a second current output terminal for outputting a second current; an offset cancellation circuit having a first controllable current source connected to the first current output terminal and a second controllable current source connected to the second current output terminal; a first transimpedance circuit having an input terminal connected to the first current output terminal and an output terminal for outputting a first voltage; a second transimpedance circuit having an input terminal connected to the second current output terminal and an output terminal for outputting a second voltage; and a first inverter having an input terminal connected to the output terminal of the first transimpedance circuit and an output terminal for outputting a first single ended output voltage.

Abstract: For performing saturation control of one or more selected colors of the image, respective color values of the selected color(s) are pre-defined. Meanwhile, a specified pixel is selected from the image. Then distance(s) between the color space coordinate of the specified pixel and the color space coordinate(s) of the selected color(s) is (are) calculated. The color values of the specified pixel are thus adjusted depending on comparing results of the distance(s) with corresponding threshold distance(s).

Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.

Abstract: A data retention device includes a first latch disposed between a data input terminal and a data output terminal for storing a data signal received from the data input terminal and transmitting the data signal through a data forward path to the data output terminal according to a clock signal in an operational mode; a second latch disposed in a branch of the data forward path between the first latch and the data output terminal for receiving the data signal in the operational mode and retaining the data signal in a sleep mode; and a first tri-state buffer disposed in the data forward path between the first latch and the branched second latch and enabled to conduct the data forward path in the operational mode and disabled to cut off the data forward path in the sleep mode according to a data retention signal.

Abstract: Method and related circuit for color depth enhancement of displays is provided. In an embodiment of the invention, when emulating an interpolated color level between a first and a second color levels the display can display, a color channel component of the first color level and another color channel component of the second color level are selected for color dithering and color depth enhancement.

Abstract: A digital-to-analog converter is coupled to a first voltage source and used for converting a digital input into an analog output. The DAC includes a voltage booster providing a first gate-source voltage and a second gate-source voltage to generate a voltage of a first level according to the first voltage source and the first gate-source voltage, and to generate a voltage of a second level according to the voltage of the first level and the second gate-source voltage; and a current-guiding circuit selectively receiving the voltage of the first level or the second level according to the digital input to generate the analog output. The first level and the second level vary with the first voltage source.

Abstract: A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.

Abstract: A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level.

Abstract: A wide-locking range phase locked loop circuit includes a decision unit and a closed loop connection comprising a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a multi-modulus divider. The decision unit receives a phase difference signal outputted from phase frequency detector and the control voltage outputted from the loop filter and determines to select a specific divisor form the plurality of divisors provided by the multi-modulus divider if the phase difference signal indicates an unlocked state and the control voltage is not within a standard voltage operation range.

Abstract: A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency Fref, the PLL outputs M voltage controlled signals with the same frequency Fvco=N*Fref and equally distributed phase differences. The rising/falling edge generating unit is for generating a rising point signal and a falling point signal corresponding to respective ones one of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals. The timing-signal generating unit coupled to the rising/falling edge generating unit is for generating a timing signal which toggles high in response to the rising point signal and toggles low in response to the falling point signal.

Abstract: A bandgap reference circuit includes a PTAT current generating circuit for generating a PTAT current; a CTAT circuit generating circuit for generating a CTAT current; a node for receiving the PTAT current and the CTAT current; and, a first resistor connected between the node and a ground, wherein a reference voltage is derived from the first resistor when a superposed current of the PTAT current and the CTAT current is flowing through the first resistor.

Abstract: A bandgap reference circuit includes an input circuit having a first FET, a second FET, and a first resistor, wherein a first node is connected to the first FET having a first threshold voltage, the first resistor is connected between a second node and the second FET having a second threshold voltage; a mirroring circuit for controlling two output currents respectively derived from the first and second nodes, and maintaining the two output currents to a specific current ratio; and an operation amplifier connected to the first node, the second node of the input circuit, and the mirroring circuit, for controlling two voltages respectively at the first and second nodes of the input circuit to a specific voltage ratio; wherein the first FET and the second FET are both operating in the subthreshold region, the first threshold voltage is larger than the second threshold voltage, and the two output currents are independent of temperature.