Abstract: An in-loop deblocking-filtering method applied to a video CODEC is provided. The method includes steps of: receiving a macroblock of pixel values outputted from a motion-compensating unit; dividing the macroblock of pixel values into a plurality of block of pixel values, and executing a data-transpose procedure to the plurality of blocks of pixel values; storing the plurality of block of pixel values, which are processed by the data-transpose procedure, in a memory buffer; executing a horizontal deblocking-filtering procedure to the macroblock of pixel values, which are stored in the memory buffer, for updating a portion of the pixel values in the macroblock; executing the data-transpose procedure to the plurality of block of pixel values stored in the memory buffer; and executing a vertical deblocking-filtering procedure to the macroblock of pixel values, which are stored in the memory buffer, for updating a portion of the pixel values in the macroblock.

Abstract: A spread spectrum clock generator includes: a phase frequency detector, for generating a phase difference signal according to a frequency divided signal and a reference signal with a reference frequency; a charge pump, for receiving the phase difference signal and generating an output current according to the phase difference signal; a loop filter, for receiving the output current and converting the output current to a voltage-controlled signal; a voltage-controlled oscillator, for receiving the voltage-controlled signal and generating a plurality of voltage-controlled output signals, wherein the plurality of voltage-controlled signals have a specific phase difference and a same voltage-controlled frequency; a frequency dividing unit, for receiving the plurality of voltage-controlled output signal and generating the frequency divided signal; and a delta-sigma modulator, for controlling the frequency dividing unit to have an equivalent divided value of (N+b)S+(N?a)(P?S) through receiving the frequency divided

Abstract: A latch includes a data input terminal for receiving a data signal; a data output terminal for outputting the data signal; a first control terminal for receiving a control signal to set or reset the data signal derived from the data output terminal; a sleep signal input terminal for receiving a sleep signal to determine a sleep mode; a first logic circuit having input terminals coupled to the data input terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data output terminal; and a second logic circuit having input terminals coupled to the data output terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data input terminal; wherein the first logic circuit or the second logic circuit ignores the first control signal in response to the sleep signal when the latch is operated in the sleep mode.

Abstract: Output stage and related method applied to source driver/chip of LCD panel. While performing dot polarization inversion for even/odd channels of LCD panel, n-channel and p-channel MOS transistors of symmetric layout are respectively adopted for alternately transmitting a positive polarization signal of higher swing range and a negative polarization signal of lower swing range from corresponding drivers of asymmetric layout to the even/odd channels, such that a layout area for alternating polarizations can be reduced. Also, the invention directly ties inputs of the output drivers to VDD or VSS so as to turn off the drivers for providing high impedance at the even/odd channels when necessary.

Abstract: Over-voltage indicator and related circuit and method. The over-voltage indicator can work with an I/O circuit of a chip for detecting over-voltage in an I/O pad and providing an indication signal accordingly. When over-voltage does not happen, the over-voltage indicator continues to detect a signal level of the I/O pad and keeps the indication signal low. Once over-voltage is detected, the over-voltage indicator pauses detecting, asserts a high level in the indication signal, and periodically resumes detecting until end of over-voltage is detected. With informing provided by the indication signal, a core cell of the chip can perform proper operation to reduce potential damage caused by over-voltage.

Abstract: The present invention is a scan flip-flop circuit with extra hold time margin. The scan flip-flop circuit includes a multiplexer, a sense amplifier and a latch. The latch includes a generation unit for generating an output signal in response to a first signal and a second signal outputted from the sense amplifier, and a storage unit receives the second signal and the output signal and maintains the output signal of the latch when the first signal and the second signal are non-activated.

Abstract: Electronic cells/cell library and related technology/method capable of achieving high integration of integrated circuits. In one embodiment, the proposed technology adopts cells with cell heights equal to a non-integer multiplication of the routing track to establish a cell library, so a layout area of each cell is reduced. Further, higher integration of integrated circuit can be achieved by applying the proposed cells in integrated circuits.

Abstract: A wide-locking range phase locked loop circuit includes a decision unit and a closed loop connection comprising a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a multi-modulus divider. The decision unit receives a phase difference signal outputted from phase frequency detector and the control voltage outputted from the loop filter and determines to select a specific divisor form the plurality of divisors provided by the multi-modulus divider if the phase difference signal indicates an unlocked state and the control voltage is not within a standard voltage operation range.

Abstract: A supply-independent biasing circuit applied to a bandgap reference circuit or a proportional to absolute temperature (PTAT) current generating circuit. The bandgap reference circuit or the PTAT current generating circuit includes a mirroring circuit, an operation amplifier, and an input circuit. The mirroring circuit including a plurality of first type FETs. The operation amplifier includes a first type FET connecting to a current input terminal of the operation amplifier. And, the supply-independent biasing circuit includes a first type FET having a gate connected to gates of the first type FETs in the mirroring circuit and having a drain acted as an output current path; and, a current mirror including a plurality of second type FETs and having a current receiving terminal connected to the output current path and having a current outputting terminal connected to the current input terminal of the operation amplifier.

Abstract: A method for overflow testing of a blind equalizer. The method uses the following steps; providing a primary located signal in a primary signaling point of a period by a signal generating loop; multiplying the primary located signal by a set of continuously decreasing signals to get a primary signal; providing a interfering located signal in a plurality of interfering signaling points of the period by a ISI generating loop, wherein the interfering signaling points are different from the primary signaling point; multiplying the interfering located signal by a set of continuously increasing/decreasing signals to get an interference signal; adding the primary signal and the interference signal to get the input signal; inputting the input signal to the blind equalizer to adapt the input signal, wherein the tap weights corresponding to the interference signal in a blind equalizer overflow.

Abstract: An input terminal of a voltage level shifter controls gates of thin oxide N-type MOS transistors with a relatively low threshold voltage. Consequently, the thin oxide N-type MOS transistor is still sufficiently turned on even when the input voltage is very low such that the voltage level shifter according to the present invention operates at high speed without distortion of the waveform of an output voltage. In order to protect the thin oxide N-type transistors, thick oxide N-type MOS transistors with gates controlled by a reference voltage level and thin oxide N-type MOS transistors with gates controlled by a relatively low voltage level are connected in series to drains of the thin oxide N-type MOS transistors to be protected. The reference voltage level is larger than the threshold voltage of the thick oxide N-type MOS transistor and equal to or smaller than a sum of twice of the relatively low voltage level and the threshold voltage of the thick oxide N-type MOS transistor.

Abstract: The invention provides an improvement in a cell structure for gate arrays. By using the cell in gate arrays, the design flexibility and the symmetry feature of the gate array can be retained. By providing transistors of different sizes, the design can possess more flexibility and more efficiency. Moreover, a denser chip layout can be completed. Thus, average wire lengths used for interconnections in the chip design may be shorter than previously possible. Also, better utilization of available chip area can be made. Thus, it becomes possible to flexibly and optimally use every area of the chip.