Abstract: A power switching circuit receives a first power, a second power and a switching signal, and generates an output power. The power switching circuit includes a first power path and a second power path. The first power path is connected with the first power. The second power path is connected with the second power. When the switching signal in a logic high level, the first power path is in a conducting state and the second power path is in a non-conducting state. Consequently, the first power is selected as the output power by the power switching circuit. When the switching signal in a logic low level, the first power path is in the non-conducting state and the second power path is in the conducting state. Consequently, the second power is selected as the output power by the power switching circuit.

Abstract: An apparatus for performing decision feedback equalizer (DFE) adaptation control is provided. The apparatus includes arithmetic circuits, slicers, sample and hold circuits, a phase detector and a control circuit for related operations. The control circuit generates parameters at least according to an error sample value and data sample values, and dynamically updates the parameters based on at least one predetermined rule to perform the DFE adaptation control. The parameters include a first parameter, another parameter and a factor adjustment parameter. Regarding at least one data pattern, the control circuit selectively replaces the error sample value with a predetermined value according to whether a temporary storage value of the error sample value conforms to a predetermined condition to control the other parameter and the first parameter, in order to prevent triggering an unstable effect and thereby prevent abnormal operations.

Abstract: A static memory apparatus and a static memory cell thereof are provided. The static memory cell includes a data latch circuit, a data write-in circuit and a data read-out circuit. The data latch circuit has a first tristate output inverting circuit and a second tristate output inverting circuit. The data write-in circuit provides a first reference voltage to a power receiving terminal of a selected tristate output inverting circuit which is one of the first and second tristate output inverting circuits, and provides a second reference voltage to an input terminal of the selected tristate output inverting circuit during a data write-in time period. The data read-out circuit generates read-out data according to a voltage at an output terminal of the second tristate output inverting circuit and the second reference voltage during a data read-out time period.

Abstract: A successive approximation analog-to-digital converter includes a first capacitance bank, a second capacitance bank, a bridge capacitor, a switch set, a comparator and a successive approximation register logic circuit. The first capacitance bank is connected with a first node. The second capacitance bank is connected with a second node. The bridge capacitor is connected between the first node and the second node. Two first input terminals of the comparator are connected with the first node and the intermediate level, respectively. An output terminal of the comparator generates a comparing signal. The successive approximation register logic circuit receives the comparing signal, and generates the switching signal and a digital data signal. The switch set selectively provides one of a low reference level, a high reference level, an input level and an intermediate level to the first capacitance bank and the second capacitance bank.

Abstract: An analog to digital converting apparatus and an initial method thereof are provided. The analog to digital converting apparatus includes a first and a second switching capacitor units, a circuit unit, a first and a second initialization switches, a third and a fourth capacitors and a logic buffer. The first and the second switching capacitor units respectively couple first capacitors and second capacitors to a first logic voltage, a second logic voltage or a first or a second input voltage according to a first control signal, and respectively generate a first and a second voltage. The circuit unit compares the first voltage and the second voltage to generate the first control signal. The first and the second initialization switches are respectively connected in series between the first and the second voltage and a common-mode endpoint. The logic buffer outputs the first or the second logic voltage to the common-mode endpoint.

Abstract: A non-volatile memory includes a memory unit. The memory unit includes a first word line, a second word line, a control line, a logic circuit, a bit line, a first cell, and a second cell. The logic circuit has a first input terminal connected to the first word line, a second input terminal connected to the second word line, and an output terminal connected to the control line. The first cell has a control terminal connected to the first word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. The second cell has a control terminal connected to the second word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line.

Abstract: A video output system at least includes a first video output terminal, a control circuit, a first digital-to-analog converter, and a first bias voltage generator. The first video output terminal is selectively connected with a first video input terminal of a display device through a signal cable. According to a constant detecting current generated by the first digital-to-analog converter, or the first bias voltage generator, the first video output terminal has a detecting voltage for indicating whether the video output system is connected with the display device. When the video output system is connected with the display device, the control circuit enables the first digital-to-analog converter but disables the first bias voltage generator. When the video output system is not connected with the display device, the control circuit disables the first digital-to-analog converter but enables the first bias voltage generator.

Abstract: A super speed USB hub includes an upstream port, a plurality of device ports, a transaction dispatching unit, a downstream buffer, a hub local packet parser, a traffic control unit, and a forwarding unit. The transaction dispatching unit is used for receiving a plurality of packets from a USB hot, wherein the plurality of packets comprise a plurality of downstream packets and a hub command packet. If the hub command packet contains a traffic management command, the hub local packet parser generates a selected target and a control mode according to the traffic management command. The traffic control unit is used for managing a downstream packet corresponding to the selected target among the plurality of downstream packets in the downstream buffer according to the selected target and the control mode.

Abstract: ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate.

Abstract: Method and associated apparatus of data extraction, including: sampling a signal and obtaining a plurality of sampled values, providing a reference sample quantity when the sampled values transit, providing a unit bit sample quantity according to the reference sample quantity, and corresponding each of the sampled values to each data bit of the signal according to the unit bit sample quantity.

Abstract: Electrostatic discharge (ESD) protection circuit including a first silicon controlled rectifier (SCR) and a trigger circuit; the trigger circuit including a first MOS transistor and a second transistor, triggering the first SCR and providing a second SCR shunt with the first SCR during ESD.

Abstract: A voltage regulator includes a constant voltage power circuit and an overcurrent protection circuit. The constant voltage power circuit generates an output voltage, an output current and a divided voltage. The overcurrent protection circuit includes a current sensing unit, a first mirroring unit, a voltage to current converting unit, a second mirroring unit, and a pull up unit. The current sensing unit generates a sensing current according to the output current. The first mirroring unit generates a first mirroring current. The first mirroring current is proportional to the output current. The voltage to current converting unit is used for converting the divided voltage into a first current. The second mirroring unit generates a second mirroring current. The second mirroring current is proportional to the second current. The pull up unit controls the output voltage and the output current according to the first mirroring current and the second mirroring current.

Abstract: ESD protection circuit with EOS immunity is provided, which includes a first connection circuit, a first EOS control circuit formed by at least a diode, and an ESD clamp respectively coupled between a pad, a first clamp node, an I/O clamp node and a second source node. When the ESD clamp detects ESD through the I/O clamp node, it is triggered to conduct from the I/O clamp node to the second source node. When the pad receives EOS, the first EOS control circuit provides a cross voltage between the first clamp node and the I/O clamp node, such that a voltage of the I/O clamp node becomes less than a characteristic voltage of the ESD clamp to prevent the ESD clamp from reverse conducting.

Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Abstract: Test system and method for analog-to-digital converter (ADC) based on a loopback architecture are provided to test an M-bit ADC. In the invention, an N-bit digital-to-analog converter (DAC) converts a digital input to a basic test signal, a segmentation circuit scales the basic test signal and superposes it with segmentation DC levels for providing corresponding segmented test signals, such that the ADC converts the segmented test signals to reflect result of testing. With the invention, practical loopback architecture of low-cost can be adopted for testing.

Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

Abstract: A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a current mirror, a control circuit, a current modulation module and a current-controlled oscillator. The current mirror has a current-controlling path and a current-outputting path. The current-controlling path and the current-outputting path are in a proportional relationship. The control circuit is used for adjusting the current flowing through the current-controlling path according to the control voltage. The current modulation module is used for generating a differential current according to the judging signal. The current-controlled oscillator is used for adjusting the phase of the second output clock signal according to the sum of the differential current and the current flowing through the current-outputting path.

Abstract: Class D amplifier is provided. The class D amplifier includes at least a block; each block includes an input circuit, an integrator, a comparator, a driving circuit and two feedback circuits. The input circuit receives a digital input to provide a differential pair of a positive and a negative input signals. The integrator receives the positive and negative input signals and a pair of positive and negative feedback signals for providing a positive error signal according to the positive input signal and the negative feedback signal, and providing a negative error signal according to the negative input signal and the positive feedback signal. The comparator compares between the positive and the negative error signals such that the driving circuit generates a driving output signal according to comparison result. The two feedback circuits respectively providing said positive and negative feedback signals according to the driving output signal.

Abstract: Field color sequential (FCS) control system applied for an FCS display device is provided. The FCS control system includes an input system, a memory and an output system. The input system, including a plurality of buffers respectively corresponding to different color channels, receives different color channel components of pixels in parallel such that components of a same color channel are stored in a same buffer. The memory, including a plurality of partitions respectively corresponding to different color channels, stores components of a same color channel to a same partition in association with triggering of rising and falling edges of a clock, respectively. The output system sequentially buffers and outputs color channel components of corresponding partitions.