Patents Assigned to FormFactor
  • High frequency printed circuit board via
    Patent number: 6538538
    Abstract: A printed circuit board (PCB) via, providing a conductor extending vertically between microstrip or stripline conductors formed on separate layers of a PCB, includes a conductive pad surrounding the conductor and embedded within the PCB between those PCB layers. The pad's shunt capacitance and the magnitudes of capacitances of other portions of the via are sized relative to the conductor's inherent inductance to optimize frequency response characteristics of the via.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: March 25, 2003
    Assignee: FormFactor, Inc.
    Inventors: Emad B. Hreish, Charles A. Miller
  • Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes
    Patent number: 6539531
    Abstract: A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and its interconnect systems are designed by selecting and specifying interconnections between component cells included in the cell library. Interconnect systems are flexibily designed to act like filters tuned to optimize desired frequency response characteristics.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: March 25, 2003
    Assignee: FormFactor, Inc.
    Inventors: Charles A. Miller, John M. Long
  • Method for manufacturing raised electrical contact pattern of controlled geometry
    Patent number: 6538214
    Abstract: An interposer includes a substrate having opposing surfaces. Conductive terminals are disposed on both surfaces, and conductive terminals on one surface are electrically connected to conductive terminals on the opposing surface. Elongate, springable, conducive interconnect elements are fixed to conductive terminals on both surfaces.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: March 25, 2003
    Assignee: FormFactor, Inc.
    Inventor: Igor Y. Khandros
  • Method and system for designing a probe card
    Publication number: 20030055736
    Abstract: A method and system for designing a probe card from data provided by prospective customers via the Internet is provided. Design specifications are entered into the system by prospective customers and compiled into a database. The collective feasibility of each set of design specifications is determined by an automated computer system and communicated to the prospective customer. If feasible, additional software enables prospective customers to create verification packages according to their respective design specifications. These verification packages further consist of drawing files visually describing the final design and verification files confirming wafer bonding pad data. Verification packages are reviewed and forwarded to an applications engineer after customer approval. An interactive simulation of probe card performance is also provided.
    Type: Application
    Filed: September 17, 2001
    Publication date: March 20, 2003
    Applicant: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Mark W. Brandemuehl, Stefan Graef, Yves Parent
  • Sockets for “springed” semiconductor devices
    Patent number: 6534856
    Abstract: Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally urging terminals of an interconnection substrate against end portions of the spring contact elements. A variety of terminal configurations are disclosed.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: March 18, 2003
    Assignee: FormFactor, Inc.
    Inventors: Thomas H. Dozier, II, Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu, David V. Pedersen, Michael A. Stadt
  • Microelectronic contact structures, and methods of making same
    Publication number: 20030049951
    Abstract: Microelectronic contact structures are fabricated by separately forming, then joining together, various components thereof. Each contact structure has three components: a “post” component, a “beam” component, and a “tip” component. The resulting contact structure, mounted to an electronic component, is useful for making an electrical connection with another electronic component. The post component can be fabricated on a sacrificial substrate, joined to the electronic component and its sacrificial substrate removed. Alternatively, the post component can be formed on the electronic component. The beam and tip components can each be fabricated on a sacrificial substrate. The beam component is joined to the post component and its sacrificial substrate is removed, and the tip component is joined to the beam component and its sacrificial substrate is removed.
    Type: Application
    Filed: July 25, 2002
    Publication date: March 13, 2003
    Applicant: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Method of assembling and testing an electronics module
    Publication number: 20030049873
    Abstract: An electronics module is assembled by demountably attaching integrated circuits to a module substrate. The module is then tested at a particular operating speed. If the module fails to operate correctly at the tested speed, the integrated circuit or circuits that caused the failure are removed and replaced with new integrated circuits, and the module is retested. Once it is determined that the module operates correctly at the tested speed, the module may be rated to operate at the tested speed and sold, or the module may be tested at a higher speed.
    Type: Application
    Filed: September 12, 2001
    Publication date: March 13, 2003
    Applicant: FormFactor, Inc.
    Inventor: Benjamin N. Eldridge
  • Process and apparatus for adjusting traces
    Publication number: 20030038850
    Abstract: Traces routed through a computer depiction of a routing area of an electronics system comprise a plurality of connected nodes. Forces are assigned to the nodes, and the nodes are moved in accordance with the forces. The forces may be based on such things as the proximity of the nodes to each other and to obstacles in the routing area. This tends to smooth, straighten and/or shorten the traces, and may also tend to correct design rule violations.
    Type: Application
    Filed: August 24, 2001
    Publication date: February 27, 2003
    Applicant: FormFactor, Inc.
    Inventor: Mac Stevens
  • Wafer-level burn-in and test
    Patent number: 6525555
    Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: February 25, 2003
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, David V. Pedersen
  • Microelectronic contact structures, and methods of making same
    Patent number: 6520778
    Abstract: Microelectronic contact structures are fabricated by separately forming, then joining together, various components thereof. Each contact structure has three components: a “post” component, a “beam” component, and a “tip” component. The resulting contact structure, mounted to an electronic component, is useful for making an electrical connection with another electronic component. The post component can be, fabricated on a sacrificial substrate, joined to the electronic component and its sacrificial substrate removed. Alternatively, the post component can be formed on the electronic component. The beam and tip components can each be fabricated on a sacrificial substrate. The beam component is joined to the post component and its sacrificial substrate is removed, and the tip component is joined to the beam component and its sacrificial substrate is removed.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: February 18, 2003
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Method of manufacturing a probe card
    Publication number: 20030025172
    Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.
    Type: Application
    Filed: March 1, 2002
    Publication date: February 6, 2003
    Applicant: FormFactor, Inc.
    Inventors: Gary W. Grube, Igor Y. Khandros, Benjamin N. Eldridge, Gaetan L. Mathieu, Poya Lotfizadeh, Chih-Chiang Tseng
  • Interconnection element with contact blade
    Publication number: 20030015347
    Abstract: An apparatus and method providing improved interconnection elements and tip structures for effecting pressure connections between terminals of electronic components is described. The tip structure of the present invention has a sharpened blade oriented on the upper surface of the tip structure such that the length of the blade is substantially parallel to the direction of horizontal movement of the tip structure as the tip structure deflects across the terminal of an electronic component. In this manner, the sharpened substantially parallel oriented blade slices cleanly through any non-conductive layer(s) on the surface of the terminal and provides a reliable electrical connection between the interconnection element and the terminal of the electrical component.
    Type: Application
    Filed: June 17, 2002
    Publication date: January 23, 2003
    Applicant: FormFactor, Inc
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Alec Madsen, Gaetan L. Mathieu
  • Planarizer for a semiconductor contactor
    Patent number: 6509751
    Abstract: A planarizer for a probe card assembly. A planarizer includes a first control member extending from a substrate in a probe card assembly. The first control member extends through at least one substrate in the probe card assembly and is accessible from an exposed side of an exterior substrate in the probe card assembly. Actuating the first control member causes a deflection of the substrate connected to the first control member.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: January 21, 2003
    Assignee: FormFactor, Inc.
    Inventors: Gaetan L. Mathieu, Benjamin N. Eldridge, Gary W. Grube
  • Method of manufacturing a probe card
    Publication number: 20030010976
    Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.
    Type: Application
    Filed: July 11, 2001
    Publication date: January 16, 2003
    Applicant: FormFactor, Inc.
    Inventors: Gary W. Grube, Igor Y. Khandros, Benjamin N. Eldridge, Gaetan L. Mathieu
  • Integrated circuit interconnect system
    Publication number: 20030006856
    Abstract: In an interconnect system for providing access to a common I/O terminal for multiple circuit devices such as drivers, receivers and electrostatic discharge (ESD) protection devices implemented on an IC, each such device is provided with a separate contact pad within the IC. The contact pads are linked to one another and to the IC I/O terminal though inductive conductors such as bond wires, metalization layer traces in the IC, or legs of a forked, lithographically-defined spring contact formed on the IC. The conductor inductance isolates the capacitance of the circuit devices from one another, thereby improving characteristics of the frequency response of the interconnect system. Also the ESD protection function is distributed among multiple ESD devices interconnected by series inductors to provide a multi-pole filter at each IC terminal.
    Type: Application
    Filed: August 2, 2002
    Publication date: January 9, 2003
    Applicant: FORMFACTOR, INC.
    Inventor: Charles A. Miller
  • Integrated circuit tester with high bandwidth probe assembly
    Patent number: 6501343
    Abstract: Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: December 31, 2002
    Assignee: FormFactor, Inc.
    Inventor: Charles A. Miller
  • Electrical contractor, especially wafer level contactor, using fluid pressure
    Publication number: 20020197895
    Abstract: An electrical interconnect assembly and methods for making an electrical interconnect assembly. In one embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact elements and a fluid containing structure which is coupled to the flexible wiring layer. The fluid, when contained in the fluid containing structure, presses the flexible wiring layer towards a device under test to form electrical interconnections between the first contact elements and corresponding second contact elements on the device under test. In a further embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact terminals and a semiconductor substrate which includes a plurality of second contact terminals.
    Type: Application
    Filed: August 15, 2002
    Publication date: December 26, 2002
    Applicant: FormFactor, Inc.
    Inventor: Benjamin N. Eldridge
  • Distributed interface for parallel testing of multiple devices using a single tester channel
    Patent number: 6499121
    Abstract: A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: December 24, 2002
    Assignee: FormFactor, Inc.
    Inventors: Richard S. Roy, Charles A. Miller
  • Electromagnetically coupled interconnect system architecture
    Publication number: 20020186106
    Abstract: An electromagnetic interconnect method and apparatus effects contactless, proximity connections between elements in an electronics system. Data to be communicated between elements in an electronic system are modulated into a carrier signal and transmitted contactlessly by electromagnetic coupling. The electromagnetic coupling may be directly between elements in the system or through an intermediary transmission medium.
    Type: Application
    Filed: May 8, 2001
    Publication date: December 12, 2002
    Applicant: FormFactor, Inc.
    Inventor: Charles A. Miller
  • Predictive, adaptive power supply for an integrated circuit under test
    Publication number: 20020186037
    Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.
    Type: Application
    Filed: July 25, 2002
    Publication date: December 12, 2002
    Applicant: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Charles A. Miller