Abstract: An electronics module is assembled by demountably attaching integrated circuits to a module substrate. The module is then tested at a particular operating speed. If the module fails to operate correctly at the tested speed, the integrated circuit or circuits that caused the failure are removed and replaced with new integrated circuits, and the module is retested. Once it is determined that the module operates correctly at the tested speed, the module may be rated to operate at the tested speed and sold, or the module may be tested at a higher speed.

Abstract: An electronic device is moved into a first position with respect to probes for making electrical contact with the device. The electronic device is then moved into a second position in which the electronic device is pressed against the probes, compressing the probes. The movement into the second position includes two components. One component of the movement tends to press the electronic device against the probes, compressing the probes and inducing a stress in the probes. The second movement tends to reduce that stress. Test data are then communicated to and from the electronic device through the probes.

Abstract: An unsingulated semiconductor wafer is provided. Electrical interconnect elements are formed on the unsingulated wafer such that the interconnect elements are electrically connected to terminals of the semiconductor dice composing the wafer. At least a portion of the interconnect elements extend beyond the boundaries of the dice into the scribe streets separating the individual dice. Thereafter, the wafer is singulated into individual dice.

Abstract: Interconnect assemblies and methods for forming and using them. In one example of the invention, an interconnect assembly comprises a substrate, a resilient contact element and a stop structure. The resilient contact element is disposed on the substrate and has at least a portion thereof which is capable of moving to a first position, which is defined by the stop structure, in which the resilient contact element is in mechanical and electrical contact with another contact element. In another example of the invention, a stop structure is disposed on a first substrate with a first contact element, and this stop structure defines a first position of a resilient contact element, disposed on a second substrate, in which the resilient contact element is in mechanical and electrical contact with the first contact element.

Abstract: An elongate, columnar micro-mechanical structure disposed along a central longitudinal axis; the structure is made up of laminated structural layers, each comprised of a structural material. The layers define a substantially rigid base portion at a proximal end of the structure, a resilient intermediate portion extending from the base portion along the central axis, and a contact tip extending from the resilient portion at a distal end of the structure. The resilient portion of the contact structure is comprised of resilient arms defined in the layers. Opposite ends of the resilient arms may be angularly offset with respect to one another around the central axis. Accordingly, when the contact structure is compressed in an axial direction, the contact tip will rotate around the central axis, while the base remains fixed, providing beneficial wiping action to the contact tip.

Abstract: A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.

Abstract: A method of forming a probe array includes forming a layer of tip material over a block of probe material. A first electron discharge machine (EDM) electrode is positioned over the layer of tip material, the EDM electrode having a plurality of openings corresponding to a plurality of probes to be formed. Excess material from the layer of tip material and the block of probe material is removed to form the plurality of probes. A substrate having a plurality of through holes corresponding to the plurality of probes is positioned so that the probes penetrate the plurality of through holes. The substrate is bonded to the plurality of probes. Excess probe material is removed so as to planarize the substrate.

Abstract: An interconnection element and a method of forming an interconnection element. In one embodiment, the interconnection element includes a first structure and a second structure coupled to the first structure. The second structure coupled with the first material has a spring constant greater than the spring constant of the first structure alone. In one embodiment, the interconnection element is adapted to be coupled to an electronic component tracked as a conductive path from the electronic component. In one embodiment, the method includes forming a first (interconnection) structure coupled to a substrate to define a shape suitable as an interconnection in an integrated circuit environment and then coupling, such as by coating, a second (interconnection) structure to the first (interconnection) structure to form an interconnection element.

Abstract: A method and apparatus for detecting an arc condition in a semiconductor test system is disclosed. While probes in a semiconductor test system are being moved into or out of contact with a semiconductor wafer, the voltage level of power supplied to selected ones of the probes is monitored. If the voltage level of the power exceeds a level that could cause an arc between the probes and the semiconductor wafer while the wafer is being moved, an indication is generated that an arc condition has been detected.

Abstract: A plurality of contact elements, such as contact bumps or free-standing spring contacts including both monolithic and composite interconnection elements, are mounted to relatively small tile substrates which, in turn, are mounted and connected to a relatively large electronic component substrate, thereby populating the electronic component with a plurality of contact elements while avoiding the necessity of yielding the contact elements directly upon the electronic component. The relatively large electronic component is suitably a space transformer component of a probe card assembly. In this manner, pressure connections can be made to an entire semiconductor wafer, at once, to provide for wafer-level burn-in, and the like. Solder balls, z-axis conductive adhesive, or compliant connections are suitably employed for making electrical connections between the tile substrates and the electronic component.

Abstract: An electronics module is assembled by demountably attaching integrated circuits to a module substrate. The module is then tested at a particular operating speed.. If the module fails to operate correctly at the tested speed, the integrated circuit or circuits that caused the failure are removed and replaced with new integrated circuits, and the module is retested. Once it is determined that the module operates correctly at the tested speed, the module may be rated to operate at the tested speed and sold, or the module may be tested at a higher speed.

Abstract: An initial graph of nodes is created within a routing space, and the number and locations of the nodes in the graph are adjusted. Links are created between nodes of the graph, and traces between specified nodes are created through the linked graph.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined in masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device. Each spring contact element has a base end, a contact end, and a central body portion. The contact end is offset in the z-axis (at a different height) and in at least one of the x and y directions from the base end. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the substrate. The spring contact elements make temporary (i.e., pressure) or permanent (e.g., joined by soldering or brazing or with a conductive adhesive) connections with terminals of another electronic component to effect electrical connections therebetween.

Abstract: Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed.

Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.

Abstract: Surface-mount, solder-down sockets are described which permit electronic components such as semiconductor packages to be releasably mounted to a circuit board. Generally, the socket includes resilient contact structures extending from a top surface of a support substrate, and solder-ball (or other suitable) contact structures disposed on a bottom surface of the support substrate. Composite interconnection elements are described for use as the resilient contact structures disposed atop the support substrate. In use, the support substrate is soldered down onto the circuit board, the contact structures on the bottom surface of the support substrate contacting corresponding contact areas on the circuit board. In any suitable manner, selected ones of the resilient contact structures atop the support substrate are connected, via the support substrate, to corresponding ones of the contact structures on the bottom surface of the support substrate.

Abstract: Microelectronic contact structures are fabricated by separately forming, then joining together, various components thereof. Each contact structure has three components: a “post” component, a “beam” component, and a “tip” component. The resulting contact structure, mounted to an electronic component, is useful for making an electrical connection with another electronic component. The post component can be fabricated on a sacrificial substrate, joined to the electronic component and its sacrificial substrate removed. Alternatively, the post component can be formed on the electronic component. The beam and tip components can each be fabricated on a sacrificial substrate. The beam component is joined to the post component and its sacrificial substrate is removed, and the tip component is joined to the beam component and its sacrificial substrate is removed.

Abstract: A multilayer printed circuit board having clustered blind vias in power layers to facilitate the routing of signal traces in signal layers. A portion of the blind vias in the power layers are grouped together to form a cluster of blind vias. Corresponding signal routing channels are provided in the signal layers and aligned with the cluster of blind vias in the power layers to permit routing of signal traces or signal circuitry therethrough. A method of manufacturing the multilayered printed circuit board includes assembling a first subassembly of power layers, forming a group of clustered power vias through the first subassembly, assembling a second subassembly of signal layers, combining the first subassembly with the second subassembly such that the clustered vias in the first subassembly align with signal routing channels in the second subassembly, forming signal vias that extend through the first and second subassemblies, and seeding or plating the power and signal vias.