Abstract: A predistortion method and apparatus are provided which use a DPD actuator (225) to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter (224) which computes second DPD coefficients u[n] with an iterative fixed-point conjugate gradient method which uses N received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, ?, ?, ?) at each predetermined interval, thereby updating the first DPD coefficients with the second DPD coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.

Abstract: A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.

Abstract: A low power clock distribution circuit system (200) includes a clock generator (201) for generating a high frequency clock signal that is supplied to a clock interconnect running to multiple lanes of an integrated circuit, each lane including a passive clock repeater circuit (e.g., 203) having a differential-mode RLC network (e.g., 301) that is shielded by an active guard ring structure (e.g., 511) and that is coupled to receive first and second input clock signals (Vip, Vin) to provide clock signal gain boosting at a predetermined frequency range and clock signal attenuation out of the operating frequency range, thereby generating the first and second output clock signals (Vop, Von) that are provided to a clocked circuit (e.g., 211).

Abstract: A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.

Abstract: A wireless communication system includes a processor that receives a downlink control information (DCI) associated with a transmission channel used for transmitting a RF signal and a control channel element index associated with the DCI. The processor determines a scrambling code based on the control channel element index for the DCI, scrambles the DCI using the scrambling code, generates a scrambled DCI, and modulates the scrambled. DCI to generate a modulated symbol. The processor uses look-up tables to determine a resource element group (REG) based on the control channel element index, map the modulated symbol to the REG, and generate a transmission frame.

Abstract: A near field communications (NFC) device is disclosed that load modulates and regulates a radio frequency (RF) signal. The NFC device includes a rectifier that rectifies the RF signal to provide a direct current voltage. The NFC device also includes a modulator that modulates a data signal. The modulator provides a first voltage when the data signal is at a first level and provides a second voltage when the data signal is at a second level. The NFC device utilizes a regulator to regulate and to load modulate the RF signal. The regulator adjusts an impedance based upon a comparison of the DC voltage provided by the regulator to the first voltage provided by the modulator for the data signal at the first level or to the second voltage provided by the modulator for the data signal at the second level.

Abstract: An assembly strip test method and adapter allows for the concurrent loading of multiple assembly strips for testing in a concurrent and/or round-robin fashion in a strip tester. The test method and adapter allows the multiple assembly strips to be loaded into a strip tester in a single load cycle, reducing assembly strip load cycle overhead. Signals generated by test probes can be used to select between the loaded assembly strips for testing via the strip tester. Parallel coupling between corresponding pins of corresponding integrated circuits of different assembly strips allows a single test probe to be used as stimulus or monitor for two or more assembly strips. In certain configurations a stackable assembly strip test adapter is used. In other configurations the integrated circuits include at least part of the assembly strip selection decoding logic.

Abstract: A method of demodulating an FSK modulated input signal whose frequency varies between first and second frequencies. The input signal is delayed by a plurality of cycles, providing a second signal. A succession of phase reference signals having respective incrementally greater phase delays relative to the input signal are provided. Samples of the phase reference signals are taken at intervals determined by the second signal. A transition between the first and second frequencies is detected when the relative values of the samples of the phase reference signals remain constant during a plurality of intervals after varying. A high speed clock is not required to perform the demodulation.

Abstract: A system for merging first and second interrupts includes first and second queue modules, first and second status modules, and first and second merger modules. The first and second queue modules receive first and second en-queue signals corresponding to the first and second interrupts, first and second de-queue signals, and generate first and second status signals. The first and second status modules receive first and second status signals, and first and second output signals, and generate first and second merge signals. The first and second merger modules receive the first and second merge signals, and generate the first and second output signals. One of the first and second output signals is indicative of the first and second en-queue signals, thereby merging the first and second interrupts into at least one of the first and second output signals.

Abstract: An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request.

Abstract: A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described.

Abstract: A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.

Abstract: A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

Abstract: An apparatus for measuring movement of an object has a quadrature incremental encoder for providing first and second phases of encoder pulses corresponding to incremental displacements of the object. A first counter counts edges of the encoder pulses according to the sense of the displacement. Clock pulse counts are also made. Acquiring movement data at periodic speed processing moments includes the decoder adjusting encoder pulse data from the first counter using a clock pulse count that is a function of a lapse of time between when the most recent edge of the encoder pulses and the speed processing moment. The clock pulse counts are reset by edges of the first and second phases of the encoder pulses when the decoder acquires the movement data.

Abstract: An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

Abstract: A method and apparatus are provided for detecting a rotor lock condition in a sensorless permanent magnet synchronous motor. A BEMF observer determines an estimated rotor speed {circumflex over (?)} and a first BEMF voltage value in an estimated rotor-related ?,? reference frame. In addition, a second estimated BEMF voltage value is calculated in a rotor-related d,q reference frame based on at least a first motor constant and an estimated rotor speed {circumflex over (?)}. After generating a BEMF error filter value from the first and second estimated BEMF voltage values and calculating a BEMF error threshold value as a function of the estimated rotor speed {circumflex over (?)} that is subject to a minimum threshold BEMF value, a rotor lock condition is detected based on at least the BEMF error filter value and the BEMF error threshold value.

Abstract: A cavity-down pressure sensor device has a pressure-sensing die that is electrically connected to a master control unit (MCU) using face-to-face bonding. Connecting the pressure-sensing die in this manner avoids the need to wire bond the pressure-sensing die to the master control unit.

Abstract: A charge pump includes a charge pump core circuit, a replica bias circuit, and a differential amplifier. The charge pump core circuit includes current source and sink circuits for charging and discharging an output node of the charge pump core circuit. The current source and current sink circuits are user programmable using bit signals to adjust a bandwidth and a phase margin of a phase-locked loop (PLL) that includes the charge pump. An impedance of the replica bias circuit varies based on the bit signals. The differential amplifier and the replica bias circuit form a feedback loop that reduces current mismatch between the current source and sink circuits.

Abstract: A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core.