Abstract: Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.

Abstract: Devices, systems and methods are provided for calibrating a transducer. One exemplary method involves determining a transfer function for the transducer based on a measured response of the transducer to an applied electrical signal, determining a set of values for a plurality of response parameters associated with the transducer based on the transfer function, determining a calibration coefficient value associated with the transducer based at least in part on the set of values and a correlation between physical sensitivity and the plurality of response parameters, and storing the calibration coefficient value in association with the transducer.

Abstract: Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal particle-containing precursor layer over a first principal surface of a first metal layer. The first metal layer and the metal particle-containing layer are then arranged in a stacked relationship with a second metal layer such that the precursor layer is disposed between the first and second metal layers. A low temperature sintering process is then carried-out at a maximum process temperature less than a melt point of the metal particles to transform the precursor layer into a sintered bond layer joining the first and second metal layers in a sintered multilayer heat sink. In embodiments wherein the sintered multilayer heat sink is contained within a heat sink panel, singulation may be carried-out to separate the sintered multilayer heat sink from the other heat sinks within the panel.

Abstract: Methods and apparatuses are provided for evaluating or testing stiction in Microelectromechanical Systems (MEMS) devices utilizing a mechanized shock pulse generation approach. In one embodiment, the method includes the step or process of loading a MEMS device, such as a multi-axis MEMS accelerometer, into a socket provided on a Device-Under-Test (DUT) board. After loading the MEMS device into the socket, a series of controlled shock pulses is generated and transmitted through the MEMS device utilizing a mechanized test apparatus. The mechanized test apparatus may, for example, repeatedly move the DUT board over a predefined motion path to generate the controlled shock pulses. In certain cases, transverse vibrations may also be directed through the tested MEMS device in conjunction with the shock pulses. An output of the MEMS device is then monitored to determine whether stiction of the MEMS device occurs during each of the series of controlled shock pulses.

Abstract: Methods for generating constraints associated with an integrated circuit design are provided. The method includes identifying, with a processor, a plurality of paths based on a floor-plan data set, each of the paths specifying a first block, a second block, and a first interconnect between the first block and the second block. Cycle time criteria is determined for each of the plurality of paths. A total delay is estimated for each of the plurality of paths based on a block-to-block delay and an in-block delay, wherein the block-to-block delay is based on the interconnect data associated with the first interconnect, and the in-block delay is based on the cell data associated with the first and second blocks.

Abstract: A predistortion method and apparatus are provided which use a DPD actuator (225) to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter (224) which computes second DPD coefficients u[n] with an iterative fixed-point conjugate gradient method which uses N received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, ?, ?, ?) at each predetermined interval, thereby updating the first DPD coefficients with the second DPD coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.

Abstract: A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.

Abstract: The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. The amplifiers described herein use a buffer that is implemented inside the device package. Specifically, the amplifiers can be implemented with a gate bias modulation buffer inside the device package, where the gate bias modulation buffer is configured to provide a modulated bias signal to a transistor gate of the amplifier.

Abstract: A low power clock distribution circuit system (200) includes a clock generator (201) for generating a high frequency clock signal that is supplied to a clock interconnect running to multiple lanes of an integrated circuit, each lane including a passive clock repeater circuit (e.g., 203) having a differential-mode RLC network (e.g., 301) that is shielded by an active guard ring structure (e.g., 511) and that is coupled to receive first and second input clock signals (Vip, Vin) to provide clock signal gain boosting at a predetermined frequency range and clock signal attenuation out of the operating frequency range, thereby generating the first and second output clock signals (Vop, Von) that are provided to a clocked circuit (e.g., 211).

Abstract: A package-on-package (PoP) device has a first package and an interposer heat spreader. The first package includes a die and a substrate. The substrate has die contact pads, top contact pads, bottom contact pads, and interconnects between the die contact pads, the top contact pads, and the bottom contact pads. The die is electrically connected to the die contact pads. The top contact pads are adapted to be electrically connected to a second package to form the PoP device. The heat spreader has a central section thermo-conductively connected to the die. The heat spreader includes at least one arm connected to the central section and extending out past an edge of the first package. The heat spreader also has openings for electrical interconnects between the first package and the second package.

Abstract: A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.

Abstract: An assembly strip test method and adapter allows for the concurrent loading of multiple assembly strips for testing in a concurrent and/or round-robin fashion in a strip tester. The test method and adapter allows the multiple assembly strips to be loaded into a strip tester in a single load cycle, reducing assembly strip load cycle overhead. Signals generated by test probes can be used to select between the loaded assembly strips for testing via the strip tester. Parallel coupling between corresponding pins of corresponding integrated circuits of different assembly strips allows a single test probe to be used as stimulus or monitor for two or more assembly strips. In certain configurations a stackable assembly strip test adapter is used. In other configurations the integrated circuits include at least part of the assembly strip selection decoding logic.

Abstract: A near field communications (NFC) device is disclosed that load modulates and regulates a radio frequency (RF) signal. The NFC device includes a rectifier that rectifies the RF signal to provide a direct current voltage. The NFC device also includes a modulator that modulates a data signal. The modulator provides a first voltage when the data signal is at a first level and provides a second voltage when the data signal is at a second level. The NFC device utilizes a regulator to regulate and to load modulate the RF signal. The regulator adjusts an impedance based upon a comparison of the DC voltage provided by the regulator to the first voltage provided by the modulator for the data signal at the first level or to the second voltage provided by the modulator for the data signal at the second level.

Abstract: A wireless communication system includes a processor that receives a downlink control information (DCI) associated with a transmission channel used for transmitting a RF signal and a control channel element index associated with the DCI. The processor determines a scrambling code based on the control channel element index for the DCI, scrambles the DCI using the scrambling code, generates a scrambled DCI, and modulates the scrambled. DCI to generate a modulated symbol. The processor uses look-up tables to determine a resource element group (REG) based on the control channel element index, map the modulated symbol to the REG, and generate a transmission frame.

Abstract: A method of demodulating an FSK modulated input signal whose frequency varies between first and second frequencies. The input signal is delayed by a plurality of cycles, providing a second signal. A succession of phase reference signals having respective incrementally greater phase delays relative to the input signal are provided. Samples of the phase reference signals are taken at intervals determined by the second signal. A transition between the first and second frequencies is detected when the relative values of the samples of the phase reference signals remain constant during a plurality of intervals after varying. A high speed clock is not required to perform the demodulation.

Abstract: A system for merging first and second interrupts includes first and second queue modules, first and second status modules, and first and second merger modules. The first and second queue modules receive first and second en-queue signals corresponding to the first and second interrupts, first and second de-queue signals, and generate first and second status signals. The first and second status modules receive first and second status signals, and first and second output signals, and generate first and second merge signals. The first and second merger modules receive the first and second merge signals, and generate the first and second output signals. One of the first and second output signals is indicative of the first and second en-queue signals, thereby merging the first and second interrupts into at least one of the first and second output signals.

Abstract: An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request.

Abstract: A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.

Abstract: A power-on-reset (POR) circuit for a system-on-chip (SOC) includes a biased switching element having a source, drain, and gate, with the source being connected to a supply voltage and the drain and gate being connected to a control line. The POR circuit further includes a first delay switching element having a source connected to a reduced supply voltage, a gate connected to the control line, and a drain, and an inverter having an input and an output, with the input being connected to the drain of the first delay switching element. The inverter includes a first CMOS inverter coupled between the supply voltage and a reference voltage. A first capacitor is coupled between the inverter input and the reference voltage. A second capacitor coupled between the inverter input and an output of the first CMOS inverter.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described.