Abstract: A method includes generating least-recently-used location information for a shared set-associative multi-access cache and next-to least-recently-used location information for the shared set-associative multi-access cache. The method includes concurrently accessing a shared set-associative multi-access cache in response to a first memory request from a first memory requestor and a second memory request from a second memory requestor based on the least-recently-used location information and the next-to least-recently-used location information. The method may include updating the least-recently-used location information and the next-to least-recently-used location information in response to concurrent access to the shared set-associative multi-access cache according to the first memory request and the second memory request.

Abstract: Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

Abstract: A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

Abstract: A true random number generator (RNG) has one or more oscillators and an output register for storing a random number output. Each of the oscillators is activated, successively, in a free-running oscillation phase, and a capture phase during which the oscillator is quiescent. The output register latches during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase. The random number output is derived from the latched end states.

Abstract: Method embodiments are provided herein for dynamically calibrating and adjusting a direct conversion receiver system. One embodiment includes applying one or more gain control signals to one or more gain elements of a receiver system, where the applying one or more gain control signals results in a gain change to the receiver system; in response to the gain change, determining whether the receiver system exhibits a DC (direct conversion) offset; and in response to a determination that the receiver system exhibits the DC offset, applying one or more DC offset correction control signals to one or more gain elements of the receiver system, where the one or more DC offset correction signals are configured to correct the DC offset.

Abstract: An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.

Abstract: A runtime classifier hardware circuit is incorporated into an electronic device for implementing hardware security by storing a support vector model in memory which is derived from pre-silicon verification data to define secure behavior for a first circuit on the electronic device; monitoring input and/or output signals associated with the first circuit using the runtime classifier hardware circuit which compares the input and/or output signals to the support vector model to detect an outlier input signal and/or outlier output signal for the first circuit; and blocking the outlier input and/or output signal from being input to or output from the first circuit.

Abstract: A method and apparatus are provided for navigating source code (112) by capturing a program trace data history (134) from a target (150) in response to execution of application executable code (123) thereon and decorating the source code blocks (252) on a graphical user interface viewer (251) by displaying an execution instance control indicator (253-255) corresponding to each detected execution instance, where an execution instance control enables control of which execution instance is displayed and an execution instance indicator displays information about the sequence of instructions that were executed at runtime in that execution instance.

Abstract: Methods for producing System-in-Packages (SiPs) containing embedded Surface Mount Device (SMD) modules are provided, as SiPs containing SMD modules. In one embodiment, the fabrication method includes positioning a semiconductor die and first preassembled SMD module, which contains a plurality of SMDs soldered to an interposer substrate, in predetermined spatial relationship. The preassembled SMD module and the semiconductor die are overmolded to yield a molded panel having a frontside at which the first preassembled SMD module and the semiconductor die are exposed. A Redistribution Layer (RDL) structure can be formed over the frontside of the molded panel containing interconnect lines electrically coupling the semiconductor die and the first preassembled SMD module. The molded panel may then undergo singulation to produce an SiP having a molded body in which the semiconductor die and the first preassembled SMD module are embedded.

Abstract: The embodiments described herein provide devices and methods for image processing. Specifically, the embodiments described herein provide techniques for blending graphical layers together into an image for display. In general, these techniques utilize multiple display control units to blend together more layers than could be achieved using a single display control unit. This blending of additional layers can provide improved image quality compared to traditional techniques that use only the blending capability of a single display control unit.

Abstract: Stacked microelectronic package assemblies are provided, as are methods for producing stacked microelectronic package assemblies. In one embodiment, the stacked microelectronic package assembly includes a base package layer onto which a stacked bridge device is stacked. The base package layer includes, in turn, a first microelectronic package and a second microelectronic package positioned laterally adjacent the first microelectronic package. The stacked bridge device extends over the first and second microelectronic packages. A first terminal of the stacked bridge device is soldered to or otherwise electrically joined to a first backside contact of the first microelectronic package, and a second terminal of the stacked bridge device is soldered to or otherwise electrically joined to a second backside contact of the second microelectronic package.

Abstract: Threshold detection for load current on a bus involves generating an output current representative of the load current using a transconductance circuit, sampling the output current during a quiescent phase of the bus to produce a sample current, generating a compensation current that is proportional to the transconductance gain associated with the transconductance circuit, where the compensation current is a function of the sample current, combining the output current, the sample current, the compensation current, and a reference current representative of a threshold value for the load current to produce a combined current, and using a discriminator during an active phase of the bus to output a first value when the sum current exceeds the threshold value and a second value when the combined current is less than the threshold value.

Abstract: A voltage regulator generates an output voltage that is a designed voltage level below the supply voltage. A reference voltage generator generates a reference voltage between ground and supply voltages. A voltage divider generates a feedback voltage between the supply and output voltages. An amplifier generates an amplifier output voltage based on a difference between the reference and feedback voltages. A buffer buffers the amplifier output voltage. A pass transistor receives the buffered voltage at its control node to sink an average load current appearing at the output node. A capacitor is connected between the supply and output voltages to provide a peak load current. A load-current-detecting transistor receives the buffered voltage at its control node to sense the load current. A compensation transistor compensates for leakage current. An internal load converts the sensed load current into a voltage control signal applied to the compensation transistor.

Abstract: A technique that reduces the startup time of a processing system authenticates a proxy for an image stored in tracked memory instead of authenticating the image stored in the tracked memory. A controller generates an alteration log authentication code based on an alteration log that is updated prior to programming the image stored in tracked memory. The controller records an alteration log authentication code in secure memory. The alteration log is indirectly related to a most recent image stored in the tracked memory. Authentication of the image of the alteration log is used as a proxy for authentication of the image stored in tracked memory, which is performed only when the tracked memory is modified. Use of the contents of the alteration log as a proxy for the contents of tracked memory accelerates the startup time of the system.

Abstract: A bit storage device, integrated circuit, and method are provided. The bit storage device comprises registers to store an actual value, an inverse value, a differential actual value, and a differential inverse value, a validation circuit including validation inputs coupled to outputs of the registers and including a validity output to provide a validity indication, and a write circuit including write circuit inputs coupled to the registers, the write circuit configured to cause, at a first clock edge, the first register to store the actual value and either the second register to store the inverse value or the fourth register to store the differential inverse value, and, at a second clock edge, the third register to store the differential actual value and the other of the second register and the fourth register to store to store the inverse value or the differential inverse value, respectively.

Abstract: A data transmission system for transmitting a data file from a server to a client device includes a processor, a memory and a network interface device. The memory includes a user space and a kernel space. The data file is stored in the kernel space. The processor receives a transmission request from the client device for transmitting the data file. The processor maps a set of virtual addresses corresponding to the data file to the user space as a mapped data file, and stores a set of physical addresses corresponding to the set of virtual addresses in a set of meta-buffers of a socket created in the user space. The network interface device retrieves the data file from the kernel space based on the set of physical addresses from the set of meta-buffers, and transmits the data file to the client device.

Abstract: A method for achieving clock timing closure in an integrated circuit (IC) design includes designing an IC using one or more component cells selected from a cell library to produce the design. A timing analysis of the design is performed to determine if timing constraints are satisfied. When a given time constraint is not satisfied, a component cell selected from the cell library is replaced with a replacement cell that has the same function and the same footprint as the replaced component cell, but has a different timing characteristic based on the phase relationship of the signal being capacitively coupled to enhance the likelihood of meeting the given time constraint. The timing analysis is repeated with the replacement cell. The process of replacing component cells and performing timing analysis may be iterative.

Abstract: A compound USB device has a controller and a N+1 component USB devices. Each component USB device Ci is assigned Ei endpoints, where 0?i?N and where each component USB device is assigned at least as many endpoints as required by its functionality. At least one component USB device is assigned the maximum number endpoints. At least one other component USB device is assigned the minimum number of endpoints, which is less than the maximum. The controller includes a RAM-share subsystem with a RAM module. The RAM module includes a USB RAM segment that has a buffer descriptor (BD) table and an endpoint data buffer. The BD table includes a corresponding entry for each assigned endpoint. At least a portion of the USB RAM segment is assigned for non-USB uses.

Abstract: In one embodiment, a self-healing baseband unit for modifying a key parameter indicator (KPI) value includes a processor that executes a real-time platform health processing agent that generates a fault alarm message based on real-time platform health data received from various components of the baseband unit. The baseband unit includes a L1 sub-system connected via a shared memory to a LL2 processing agent. The L2 processing agent includes a data plane processing module for generating control data and a scheduling module. The scheduling module includes a scheduler trade-off module for generating a trade-off value based on the KPI value and the fault alarm message, and an air interface scheduler that modifies primary uplink and downlink transmission schedules based on the trade-off value, a bearer QoS value, and the control data. The KPI is modified by transmission and reception using the modified uplink and downlink transmission schedules.

Abstract: A method for determining the sensitivity of an analog output node of a mixed-signal module on a system on a chip (SoC) to noise coupling on the analog input nodes of the mixed-signal module includes (i) selecting an IP block for testing, (ii) selecting the output node, (iii) compiling a list of input nodes for testing, (iv) for each input node of the list, providing excitation signals at different frequencies, (v) for each provided excitation signal, determining the output node's noise sensitivity, and (vi) if any individual and/or cumulative noise sensitivity result exceeds a preset threshold, then modifying the SoC design to take corrective action.