Abstract: A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.

Abstract: An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

Abstract: An apparatus for measuring movement of an object has a quadrature incremental encoder for providing first and second phases of encoder pulses corresponding to incremental displacements of the object. A first counter counts edges of the encoder pulses according to the sense of the displacement. Clock pulse counts are also made. Acquiring movement data at periodic speed processing moments includes the decoder adjusting encoder pulse data from the first counter using a clock pulse count that is a function of a lapse of time between when the most recent edge of the encoder pulses and the speed processing moment. The clock pulse counts are reset by edges of the first and second phases of the encoder pulses when the decoder acquires the movement data.

Abstract: A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

Abstract: A method and apparatus are provided for detecting a rotor lock condition in a sensorless permanent magnet synchronous motor. A BEMF observer determines an estimated rotor speed {circumflex over (?)} and a first BEMF voltage value in an estimated rotor-related ?,? reference frame. In addition, a second estimated BEMF voltage value is calculated in a rotor-related d,q reference frame based on at least a first motor constant and an estimated rotor speed {circumflex over (?)}. After generating a BEMF error filter value from the first and second estimated BEMF voltage values and calculating a BEMF error threshold value as a function of the estimated rotor speed {circumflex over (?)} that is subject to a minimum threshold BEMF value, a rotor lock condition is detected based on at least the BEMF error filter value and the BEMF error threshold value.

Abstract: A cavity-down pressure sensor device has a pressure-sensing die that is electrically connected to a master control unit (MCU) using face-to-face bonding. Connecting the pressure-sensing die in this manner avoids the need to wire bond the pressure-sensing die to the master control unit.

Abstract: A charge pump includes a charge pump core circuit, a replica bias circuit, and a differential amplifier. The charge pump core circuit includes current source and sink circuits for charging and discharging an output node of the charge pump core circuit. The current source and current sink circuits are user programmable using bit signals to adjust a bandwidth and a phase margin of a phase-locked loop (PLL) that includes the charge pump. An impedance of the replica bias circuit varies based on the bit signals. The differential amplifier and the replica bias circuit form a feedback loop that reduces current mismatch between the current source and sink circuits.

Abstract: A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core.

Abstract: An integrated circuit (IC) die has side input/output (IO) pads located along each side of the die interior. Each die corner has a corner IO pad. The side IO pads adjacent to the corner IO pads have shortened passivation regions in the top metal layer (TML) that define TML access regions. TML traces run through the TML access regions to connect the corner IO pads to the die interior. Providing corner IO pads enables an IC die to have up to four more IO pads than a comparable conventional IC die that does not have any corner IO pads, or an IC die to have the same number of IO pads within a smaller overall footprint.

Abstract: A 24-transistor D flip-flop circuit operates in a sampling mode when a clock signal has a first voltage state, and a holding mode when the clock signal has a second voltage state. The flip-flop circuit includes an internal control node coupled to a reference voltage node by way of a transistor controllable to couple the internal control node to the reference voltage node when the clock signal has the second voltage state. The flip-flop has very low power dissipation as it includes a 4-transistor change-sense component to detect changes in input data. The change-sense component is coupled in series with the transistor and receives an indication of an input voltage state of the flip-flop circuit and an indication of an output voltage state of the flip-flop circuit, and inhibits toggling of the internal control node if the indicated input voltage state and the indicated output voltage state are the same.

Abstract: A sink apparatus for receiving and playing back multimedia data receives data frames and discards data frames from its processing pipeline in order to reduce latency if it is determined that an amount of media data buffered in one or more portions of the processing pipeline during a fixed playback time period is above a threshold value. The threshold value and therefore the extent to which data frames are discarded can be varied in order to balance latency and quality of the displayed multimedia data.

Abstract: A level shifter in a primary voltage domain has a control module receiving an input signal from a secondary voltage domain for controlling operation of the level shifter. The control module includes a complementary pair of transistors and a first native transistor connected in a series current conduction path in the primary voltage domain. The complementary pair of transistors have gates connected to receive the input signal and the first native transistor has a gate connected to limit to a leakage current the current in the series current conduction path.

Abstract: Manufacturing of magnetometer units employs a test socket having a substantially rigid body with a cavity therein holding an untested unit in a predetermined position proximate electrical connection thereto, wherein one or more magnetic field sources fixed in the body provide known magnetic fields at the position so that the response of each unit is measured and compared to stored expected values. Based thereon, each unit can be calibrated or trimmed by feeding corrective electrical signals back to the unit through the test socket until the actual and expected responses match or the unit is discarded as uncorrectable. In a preferred embodiment, the magnetic field sources are substantially orthogonal coil pairs arranged so that their centerlines coincide at a common point within the predetermined position. Because the test-socket is especially rugged and compact, other functions (e.g., accelerometers) included in the unit can also be easily tested and trimmed.

Abstract: Embodiments of the present disclosure can be used to produce smaller, more compact antenna drivers at a reduced cost. Systems and methods for integrating components of an antenna driver with components of a shunt regulator and clamp are provided. By combining these components according to embodiments of the present disclosure, transistor count in an antenna driver can be reduced. This integrated device advantageously allows antenna driver functionality, regulator functionality, and clamp control functionality to be provided at a reduced manufacturing cost and with reduced real estate.

Abstract: A content addressable memory device includes a first memory cell having three programmable resistive elements coupled in parallel. The first terminals of the first, second, and third programmable resistive elements are coupled to a first node, the second terminal of the first programmable resistive element coupled to a first source line voltage, the second terminal of the second programmable resistive element coupled to a second source line voltage, and the second terminal of the third programmable resistive element coupled to a first supply voltage. A first access transistor includes a first current electrode coupled to a bit line; a second current electrode coupled to the first node, and a control electrode coupled to a word line. A match line transistor includes a first current electrode coupled to a match line; a second current electrode coupled to a second supply voltage and a control electrode coupled to the first node.

Abstract: A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.

Abstract: In a touch interface, a sensor provides an output signal that is a function of a sensed capacitance. The sensor includes a charger for repetitively applying first and second voltages to charge the sensed capacitance to first and second charge values in first and second phases respectively. A sampler includes a first current mirror for providing first and second sample current signals that are a function of the first and second charge values respectively. An accumulator uses an accumulator signal to provide the output signal. The accumulator repetitively uses the first and second sample current signals differentially to modify a charge on an accumulator capacitor and provide the accumulator signal. The accumulator signal is a progressive function of the sensed capacitance but cancels noise in the first and second sample signals at frequencies less than a repetition rate of operation of the accumulator.

Abstract: An integrated circuit (IC) and associated method support using a pre-use configuration for determining an initial/preferred operational mode for the IC from plural operational modes that may be entered following power-up cycles of the IC. The initial/preferred operational mode can be determined after the design phase of the IC so that, during IC operation, wasted power or delay are not incurred by first requiring that the IC power up in a default operational mode and subsequently run executive code to reprogram the IC to enter an operational mode that is preferred for the application for which the IC is being used by the IC integrator/user. The configurations determine clock frequencies and/or power levels for core processing and/or peripheral modules and allow the same IC design/die to be targeted to a spectrum of different power usage/performance applications by the integrator/user.

Abstract: A method and apparatus are provided for manufacturing a packaged electronic device (200) which includes a carrier substrate (120) in which conductive interconnect paths (122) extend between first and second opposed surfaces, an integrated circuit die (125) affixed to the first surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, and an array of conductors (110), such as BGA, LGA, PGA, C4 bump or flip chip conductors, affixed to the second surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, where the array comprising a signal feed ball (112) and an array of shielding ground balls (111) surrounding the signal feed ball.

Abstract: Methods and a system are described for generating a waveform for transmitting data over a channel divided into a plurality of adjacent frequency subcarriers. One method includes receiving a plurality of data bits, each destined for a different receiver of a plurality of receivers. For each received data bit, the method further includes coding the data bit using a unique spreading code of a first set of spreading codes to generate a corresponding group of multiple copies of a data symbol. Additionally, the groups of data symbols, corresponding to the plurality of data bits, are interleaved to generate a sequence of interleaved data symbols, and the sequence of interleaved data symbols is mapped to the plurality of adjacent frequency subcarriers to generate a waveform symbol.