Abstract: A semiconductor device comprises a power transistor and a sense transistor. The power transistor conducts a power transistor current. The sense transistor conducts a sense transistor current substantially proportional to of the power transistor current. The power transistor and the sense transistor have drain source and a gate terminals, of which those of the sense transistor are arranged to be biased to those of the power transistor, respectively. The power transistor and the sense transistor each comprise: an inner region of type P?; an N-type buried layer; an N-type isolating barrier surrounding the inner region partially; an N-type source region in the inner region; an N-type drain region in the inner region. A barrier-to-drain connector connects the isolating barrier to the drain region, the one of the sense transistor has an electrical resistance which is higher than the resistance of the barrier-to-drain connector of the power transistor.

Abstract: A method includes applying a compressive force against MEMS structures at a front side of a MEMS wafer using a protective material covering at least a portion of the front side of the MEMS wafer. The method further includes concurrently dicing through the protective material and the MEMS wafer from the front side to produce a plurality of MEMS dies, each of which includes at least one of the MEMS structures. The protective material is secured over the front side of the MEMS wafer to apply pressure to the protective material, and thereby impart the compressive force against the MEMS structures to largely limit movement of the MEMS structures during dicing. A tack-free surface of the protective material enables its removal following dicing.

Abstract: A method of making a semiconductor device forms anchors for one or more layers of material. The method includes depositing a first layer of material on a substrate, applying a mask over the first layer of material to mask nanoparticle-sized areas of the first material, removing portions of the first layer of material to form a first set of recesses around the nanoparticle-sized areas of the first material, depositing a second layer of material in the recesses and over the nanoparticle-sized areas so that a second set of recesses is formed in a top surface of the second layer of material, and forming a component of the semiconductor device over the second layer of material. Material of a bottom surface of the component is included in the second set of recesses.

Abstract: A microelectromechanical systems (MEMS) die includes a substrate having a first substrate layer, a second substrate layer, and an insulator layer interposed between the first and second substrate layers. A structure is formed in the first substrate layer and includes a platform upon which a MEMS device resides. Fabrication methodology entails forming the MEMS device on a front side of the first substrate layer of the substrate, forming openings extending through the second substrate layer from a back side of the second substrate layer to the insulator layer, and forming a trench in the first substrate layer extending from the front side to the insulator layer. The trench is laterally offset from the openings. The trench surrounds the MEMS device to produce the structure in the first substrate layer on which the MEMS device resides. The insulator layer is removed underlying the structure to suspend the structure.

Abstract: A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures.

Abstract: An electrostatic discharge (ESD) device is disclosed having two PNP transistors. During a high-voltage ESD event a parasitic NPN transistor couples to one of the two PNP transistors to provide ESD protection.

Abstract: A method of undervoltage detection includes detecting a voltage level for a power supply of a system, placing the system in an undervoltage state if the voltage level is below an undervoltage threshold, activating a load of the system at a first power level if the detected voltage level exceeds a first activation threshold and if the system resides in the undervoltage state, and activating the load at a second power level if the detected voltage level exceeds a second activation threshold.

Abstract: In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. The method includes resuming execution in delayed lockstep of the redundant computing modules in response to the handling of the error.

Abstract: Flip-flop cells that enable time borrowing during the design of the IC to improve setup times while avoiding introducing meta-stability, and alternatively to avoid hold time violations. The flip-flop cells are connected with logic cells in functional data paths. The flip-flop cell has a clock signal controlling both its input and output. A selective delay cell selectively delays either a data signal input to the flip-flop cell or the clock signal controlling the flip-flop cell. The selectively delayed signal adjusts the timing (setup, hold and clock-to-output) of the data path.

Abstract: A structure to improve saw singulation quality and wettability of integrated circuit packages (140) is assembled with lead frames (112) having half-etched recesses (134) in leads. In one embodiment, the structure is a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package (140) that includes a semiconductor device encapsulated in a package body (142) having a plurality of leads (120). Each lead has an exposed portion external to the package. There is recess (134) at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material (300).

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes both a static wire mesh and an active wire mesh. The wire meshes can be formed in the same layer over the circuits to be protected or in different layers. The wire meshes also may cover the entire chip area or only predetermined areas, such as over secure memory and register areas. The wire meshes are connected to a tamper detection module, which monitors the meshes and any signals transmitted via the meshes to detect attempts to access the protected circuits via micro-probing.

Abstract: The present application relates to an apparatus for detecting software interference and the method of operating thereof. A processor and at least one shared resource form a computing shell to execute a first, functional safety critical application and at least one second application in time-shared operation. One or more performance counters are provided to adjust a counter value in response to a performance related event. A reference value storage stores one or more threshold values, each of which is associated with one of the performance counters. A comparator receives the performance counter values, compares the performance counter values with the respective threshold values and generates at least one comparison signal in response to results of the comparisons. An interference indication generator receives the at least one comparison signal and generates at least one interference indication in response to the at least one received comparison signal.

Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.

Abstract: A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.

Abstract: A data processing device, comprising a processing unit and a test control unit connected to the processing unit, is described. The processing unit and the test control unit are arranged to: start a logic test of the processing unit; detect a test abort event; and, in response to the test abort event, perform an event response action which comprises aborting the logic test and booting the processing unit, said booting including executing an event handling routine. The event response action may comprise setting a reset vector to an address of the event handling routine. System availability may thus be improved. In particular, the delay between capturing an asynchronous signal and responding to it may be reduced. The test abort event may, for example, be an asynchronous event having certain pre-defined characteristics. A method of operating a data processing device is also described.

Abstract: A nonvolatile memory includes a memory array having a plurality of memory cells, a select gate driver configured to provide a select gate voltage to a select gate of a first memory cell of the plurality of memory cells, and a control gate driver configured to use the select gate voltage to provide a control gate voltage to a control gate of a second memory cell of the plurality of memory cells.

Abstract: A circuit arrangement for Logic Built-In Self-Test (LBIST) includes a clock source configured to generate a system clock, a first clock division circuitry configured to derive a first punched-out clock and a plurality of scan chains operable at the first punched-out clock. Each scan chain has an associated output circuitry responsive to a leading edge of the first punched-out clock. The circuit arrangement includes a second clock division circuitry configured to derive a second punched-out clock. The second punched-out clock has a delay of one or more system clock periods relative to the first punched-out clock. A compacting logic is configured to compact signals received from the scan chains. A sequential retiming element connects the compacting logic to an input circuitry of a MISR. The sequential retiming element is responsive to a trailing edge of the second punched-out clock. The input circuitry is responsive to a leading edge of the second punched-out clock.

Abstract: A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

Abstract: An EDA tool for verifying timing constraints of an integrated circuit (IC) design includes a processor and a memory that stores register transfer level (RTL) code of the IC design and a timing constraint file. The processor generates a netlist based on the RTL code, and identifies asynchronous clock paths, false paths and multi-cycle paths in the netlist using the timing constraint file. The processor then inserts buffer cells for logic cells in the netlist. The processor also inserts buffer cells in the asynchronous clock paths, false paths, and multi-cycle paths. The processor delay annotates logic cells and clock delay cells with a zero delay value and the buffer cells with known delay values. The processor generates a modeled standard delay format (SDF) file and performs a gate level simulation (GLS) using the modeled SDF file.

Abstract: A programmable buffer system includes a plurality of programmable resources. Each of the programmable resources includes, in an unconfigured state, a buffer with multiple entries, an input multiplexer, and an output multiplexer. Configuration information registers specify whether each of the programmable resources is configured as one of a group consisting of: a logic block, a shift register, and a state record, and which of a plurality of timer signals is to be provided to each of the plurality of programmable resources.