Abstract: A phase lock loop monitor circuit is disclosed. The phase lock loop monitor circuit may include a coarse tuning circuit operable to generate a coarse tune failure indicator, a frequency target lock detector circuit operable to generate a frequency target failure indicator, a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator, and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.

Abstract: A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a gate region fill material over the NVM region and the logic region. The gate region fill material is patterned over the NVM region to leave a first patterned gate region fill material over the NVM region. An interlayer dielectric is formed around the first patterned gate region fill material. A first portion of the first patterned gate region fill material is removed to form a first opening and leaving a second portion of the first patterned gate region fill material. The first opening is laterally adjacent to the second portion. The first opening is filled with a charge storage layer and a conductive material that includes metal overlying the charge storage layer.

Abstract: A sensing device includes a sensor die having a sensing region formed at a first surface of the sensor die. The sensing device further includes an encapsulant covering the sensing die, the encapsulant having a cavity formed therein, wherein the cavity exposes the sensing region. A sensitive membrane material is deposited within the cavity over the sensing region. A method of manufacturing sensing devices entails mounting a plurality of sensing dies to a carrier, encapsulating the dies in an encapsulant, forming cavities in the encapsulant, the cavities exposing a sensing region of each sensor die, and depositing the sensitive membrane material within each of the cavities. The encapsulating and forming operations can be performed simultaneously using a film-assisted molding (FAM) process, and the depositing operation is performed following FAM at an ambient temperature that is lower than the temperature needed to perform FAM.

Abstract: A bi-directional trench field effect power transistor. A layer stack extends over the top surface of the substrate, in which vertical trenches are present. An electrical path can be selectively enabled or disabled to allow current to flow in opposite directions through a body located laterally between the first and second vertical trenches. A shallow trench, more shallow than the first vertical trench and the second vertical trench is located between the first vertical trench and the second vertical trench and extend in the vertical direction from the top layer of the stack into the body, beyond an upper boundary of the body. The body is provided with a dopant, the concentration of the dopant is at least one order of magnitude higher in a region adjacent to the shallow trench than near the first vertical trench and the second vertical trench.

Abstract: The present application relates to an orthogonal frequency division multiplexing (OFDM) receiver and a method of operating the receiver for performing a cell search. A coarse correlator block is provided to detect one cell out of a by plurality of wireless communication cells by determining first correlation metric values by applying a partial correlation comprising part-wise correlating sample data with each one of a first set of phase-rotated reference sequences and non-coherent combining. The maximum of the first correlation values yields to a cell identifier value. A fine correlator block is provided to estimate a fine time offset value for the one wireless communication cell by determining second correlation values by applying a correlation comprising correlating the he sample data with each one of a second set of phase-rotated reference sequences. The maximum of the second correlation values value yields to a fine time offset.

Abstract: A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo decoder engines arranged to operate in parallel. A loader receives and separates LLRs into systematic and parity data and stores them into a portion of a word per cycle until a word is full in a corresponding one of the systematic memory and parity memory. The turbo decoder engines read the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle. The data can be rearranged within the words in an order format for the turbo decoder engines to later read them by providing sub-words corresponding to respective ones of the plurality of turbo decoder engines.

Abstract: A system for steering data packets in a communication network that includes compute nodes having processors for executing application and service virtual machines (VMs), and traffic steering accelerators. A virtual local area network-identifier (VLAN-ID) assignment module generates records and associates the records with the service VMs. Each record includes an input VLAN-ID, an output VLAN-ID, and a port number corresponding to one of the service VMs. A service-chaining module generates chaining rules associated with n-Tuples. A traffic steering controller generates a chain of the records based on the service chaining rules. The traffic steering accelerator then steers the data packets based on the input and output VLAN-IDs included in the data packet.

Abstract: A decentralized method for IPSec processing in virtual environments includes assigning a unique identifier to each of a set of compute nodes. Each compute node can emulate one or more virtual machines that generate IP packets for forwarding over a network (e.g., the Internet). An IP packet, received from a trusted source at a compute node, is encrypted and a trailer is appended to the encrypted packet. The trailer includes the unique identifier of the compute node. The encrypted packet with appended trailer is forwarded to a secure gateway that can perform an anti-replay check using stored parameters corresponding to the unique identifier in the trailer. In inbound processing, the unique identifier is inserted into a trailer appended to an encrypted packet by the security gateway and a VPN server directs the incoming encrypted packet to the appropriate compute node for forwarding to the virtual machine.

Abstract: An apparatus for debugging operational code of a target program comprises a memory storing the operational code and a set of instructions representing a debugger program for debugging the operational code. A microprocessor is configured to execute the operational code and the debugger program. The debugger program can inject a jump to a breakpoint handling routine into the operational code and let a compiler program create code pieces for the breakpoint handling routine.

Abstract: There is disclosed an apparatus for external access to core resources (211,212) of a processor (2) comprising a processing core (21), a shared memory (22), and a multiple paths Direct Memory Access, DMA, controller (23). Access to core critical resources can be performed while the core is executing an application program. The proposed apparatus comprises a Manager module (13) which is operable to setup the DMA controller to copy the assigned core resources via allocated DMA channel into a safe memory region. Further, an Observer module (14) is operable to read the transferred data and make the correlation on the host apparatus side. This allows accessing data used by the core via the DMA controller into, e.g., a run-time debugger accessible region.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).

Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having multiple vertically-stacked inertial transducer elements (101B, 110D) formed in different layers of a multi-layer semiconductor structure (100) and one or more cap devices (200, 300) bonded to the multi-layer semiconductor structure (100) to protect any exposed inertial transducer element from ambient environmental conditions.

Abstract: Circuits and methods are provided for compensating an offset voltage measured between a first transistor and a second transistor of a sense amplifier circuit that is configured to sense a bit line signal during a sensing phase. The first transistor and the second transistor are cross-coupled. The first transistor is coupled to a first capacitor and the second transistor is coupled to a second capacitor. The first capacitor is further coupled to the second capacitor, and the first and second capacitors are coupled to a third transistor. The first capacitor applies a first bias voltage to the first transistor during a pre-sensing phase prior to the sensing phase, and the second capacitor applies a second bias voltage to the second transistor during the pre-sensing phase.

Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A method may include providing the die carrier, melting the die attach material at a temperature in excess of 240° C. to attach the die to the surface of the die carrier to form a sub-assembly, attaching the sub-assembly to a leadframe, electrically interconnecting the die and the leadframe, and enclosing at least portions of the die and the leadframe to form a packaged device.

Abstract: A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant.

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

Abstract: Embodiments of inductive communication devices include first and second galvanically isolated IC die and a dielectric structure. Each IC die has a coil proximate to a first surface of the IC die. The IC die are arranged so that the first surfaces of the IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. The dielectric structure is positioned within the gap directly between the first and second coils, and a plurality of conductive structures are positioned in or on the dielectric structure and electrically coupled with the second IC die. The conductive structures include portions configured to function as bond pads, and the bond pads may be coupled to package leads using wirebonds. During operation, signals are conveyed between the IC die through inductive coupling between the coils.

Abstract: A method of provisioning an integrated circuit with decoupling capacitance includes identifying in an initial design of the integrated circuit lacking decoupling elements, a standard cell instance satisfying a transient power or frequency switching criteria. Based on a transient power characteristic of the standard cell instance, a decoupling capacitance requirement for the standard cell instance is determined. The decoupling capacitance requirement indicates a capacitance sufficient to bring the standard cell instance into compliance with a stability constraint on a supply voltage node of the standard cell instance. A decoupling capacitor satisfying the decoupling capacitance requirement is provisioned by appending an appropriate sized decap transistor having one or more gate electrode elements to the standard cell instance.

Abstract: A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.

Abstract: A circuit includes a first transistor having a first current electrode coupled to a first power supply node, a second current electrode coupled to a switching node; a second transistor having a first current electrode coupled to the switching node, a second current electrode coupled to a second power supply node; an inductor having a first terminal coupled to the switching node, a second terminal coupled to an output node; a third transistor having a first current electrode coupled to the output node, a second current electrode coupled to the switching node; a driver circuit configured to transition the switching node from a first voltage to a second voltage by turning on the third transistor to couple the output node to the switching node during a first time period, turning on the first transistor to couple the first power supply node to the switching node during a second time period.