Abstract: The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

Abstract: A dual-band Doherty amplifier and method therefor are provided. The dual-band Doherty amplifier includes a first amplifier gain element, a first transmission line coupled to a first output of the first amplifier gain element, a second amplifier gain element, a second transmission line coupled to a second output of the second amplifier gain element, and a controller configured, when a signal to be amplified is in a first band, to provide a first bias signal to a first bias input of the first amplifier gain element and a second bias signal to a second bias input of the second amplifier gain element and, when the signal is in a second band, to provide the second bias signal to the first bias input of the first amplifier gain element and the first bias signal to the second bias input of the second amplifier gain element.

Abstract: An embodiment of an amplifier includes N (N>1) switch-mode power amplifier (SMPA) branches. Each SMPA branch includes two drive signal inputs and one SMPA branch output. A module coupled to the amplifier samples an input RF signal, and produces combinations of drive signals based on the samples. When an SMPA branch receives a first combination of drive signals, it produces an output signal at a first voltage level. Conversely, when the SMPA branch receives a different second combination of drive signals, it produces the output signal at a different second voltage level. Finally, when the SMPA branch receives a different third combination of drive signals, it produces the output signal at a voltage level of substantially zero. A combiner combines the output signals from all of the SMPA branches to produce a combined output signal that may have, at any given time, one of 2*N+1 quantization states.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device includes gate structures within a semiconductor substrate, a shielding structure within the semiconductor substrate that includes a first portion underlying a first gate structure and a second portion proximate an end of the gate structures, and a conductive structure overlying the second portion of the shielding structure and an end region of the semiconductor substrate. The conductive structure provides an electrical connection between the second portion of the shielding structure and the end region of the semiconductor substrate residing between the gate structures proximate the end of the gate structures.

Abstract: A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.

Abstract: A computer system for generating an optimized program code from a program code having a loop with an exit branch, wherein the computer system comprises a processing unit, wherein the processing unit is arranged to convert an exit instruction of the exit branch into a predicated exit instruction, wherein the processing unit is arranged to determine common dependencies within the loop, wherein the processing unit is arranged to generate modified dependencies by adding additional dependencies to the common dependencies, and wherein the processing unit is arranged to apply an algorithm that uses software pipelining for generating an optimized program code for the loop based on the modified dependencies.

Abstract: An apparatus and corresponding method are provided to control a switched current circuit by switching the switched current circuit into an ON-state, waiting an amount of waiting an amount of time tB after the current within the switched current circuit increases above a current threshold, and switching the switched current circuit into an OFF-state after waiting the time tB. Further, a duration of time tA1 between switching the switched current circuit in the OFF-state and the point at which the current within the switched current circuit decreases below the current threshold is determined, and the method includes waiting a time tA2 after the current within the switched current circuit decreased below the current threshold, the time tA2 based at least in part on the time tA1, after which the switched current circuit is switched into the ON-state.

Abstract: A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides. The deuterated hydride can be used to form an amorphous semiconductor material that is annealed to form nanoparticles to be incorporated into the charge-storing layer.

Abstract: A method for 3D device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a set of through-holes extending from a first surface of the first die to a second surface of the first die. The second die includes a third surface and a set of metal posts. The first die and the second die are stacked such that the third surface of the second die faces the second surface of the first die, and each metal post extends through a corresponding through-hole to a point beyond the first surface of the first die, electrically coupling the first die and the second die.

Abstract: An amplifier module includes a module substrate. Conductive interconnect structures and an amplifier device are coupled to a top surface of the module substrate. The interconnect structures partially cover the module substrate top surface to define conductor-less areas at the top surface. The amplifier device includes a semiconductor substrate, a transistor, a conductive feature coupled to a bottom surface of the semiconductor substrate and to at least one of the interconnect structures, and a filter circuit electrically coupled to the transistor. The conductive feature only partially covers the semiconductor substrate bottom surface to define a conductor-less region that spans a portion of the bottom surface. The conductor-less region is aligned with at least one of the conductor-less areas at the module substrate top surface. The filter circuit includes a passive component formed over a portion of the semiconductor substrate top surface that is directly opposite the conductor-less region.

Abstract: A sigma-delta (??) analog-to-digital converter (ADC) comprises a main ?? modulator configured to receive an analog input signal at a main ?? modulator input and to provide a main digital output signal representative of the analog input signal and an auxiliary ?? modulator configured to receive an auxiliary input signal at an auxiliary ?? modulator input and to provide an auxiliary digital output signal, wherein the ?? ADC comprises a shared integrator stage, the shared integrator stage is configured to be used by the main ?? modulator and the auxiliary ?? modulator, wherein, alternatingly, the shared integrator stage is selectively communicatively coupled to receive the analog input signal when configured to be used by the main ?? modulator and selectively communicatively coupled to receive the auxiliary input signal when configured to be used by the auxiliary ?? modulator.

Abstract: An LDMOS device implements a substrate having a buried isolation layer, a first well region that incorporates two stacked sub-regions to provide a PN junction with a RESURF effect, and a second well region laterally offset from the first well region. A source region is formed in one of the well regions and a drain region is formed in the other well region. An extension region is disposed immediately adjacent to the first well region and laterally distal to the second well region. An extension biasing region is formed at least partially within the extension region, and is separated from the first well region by a portion of the extension region. One or more metallization structures electrically couple the extension biasing region to the one of the source/drain region in the second well region. A gate structure at least partially overlaps both well regions.

Abstract: An operating voltage and reference current are adjusted in a memory device. At least a portion of an array of memory cells is preconditioned to an erased state using an erase verify voltage on word lines coupled to the memory cells and a first reference current in sense amplifiers coupled to bit lines for the array. A test reference current is set for the sense amplifiers. A bitcell gate voltage is set on the word lines to a present overdrive voltage. The at least a portion of the array is read. If any of the memory cells in the at least a portion of the array are read as being programmed, the present overdrive voltage is increased until none of the memory cells in the at least a portion of the array are read as being programmed.

Abstract: A semiconductor structure includes a lead frame having a flag and a plurality of leads, a semiconductor die attached to a first major surface of the flag, and a plurality of re-routed lead fingers attached to the lead frame. The plurality of leads has a first pitch. The first end of each re-routed lead finger is attached to a lead of the plurality of leads. Each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from the flag of the lead frame. The second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch.

Abstract: Embodiments include devices and methods of their manufacture. A device embodiment includes a package housing, at least one electronic circuit (e.g., a sensor circuit), a first material, and a second material. The package housing includes a cavity that is partially defined by a cavity bottom surface, and the cavity bottom surface includes a mounting area and a non-mounting area. The at least one electronic circuit is attached to the cavity bottom surface over the mounting area. The first material has a relatively high, first modulus of elasticity, and covers the non-mounting area. The second material has a relatively low, second modulus of elasticity, and is disposed over the first material within the cavity.

Abstract: An electronic device comprises a secured module arranged to store secured data. A component outside the secured module has a normal operating mode with a normal mode operating voltage. An interface is arranged to provide access to the secured module. A voltage monitoring unit is connected to the component and arranged to monitor an operating voltage Vsup of the component. An interface control unit is connected to the voltage monitoring unit and the interface. The interface control unit is arranged to inhibit access to the secured module through the interface when the operating voltage is below a predetermined secure access voltage level, the secure access voltage being higher than the normal mode operating voltage.

Abstract: A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal pillars. The first die and the second die are stacked such that each metal pillar extends from a surface of the second die to a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal pillars and the corresponding pads.

Abstract: An integrated circuit having normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal (204) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.

Abstract: A spread-spectrum clock (SSC) generator for generating an SSC signal. The SSC generator has a first up/down counter that operates for a fixed, first duration (t1), a first PRBS generator that operate for a variable, second duration (t2), a second up/down counter that operates for a fixed, third duration (t3), and a second PRBS generator that operates for a variable, fourth duration (t4). A state machine sequentially triggers the first counter and the first PRBS generator to generate a positive portion of a cycle of the SSC signal and then sequentially triggers the second counter and the second PRBS generator to generate a negative portion of the cycle of the SSC signal. For a set of parameters stored in configurable registers, the first and third durations are fixed from cycle to cycle, while the second and fourth durations vary from cycle to cycle.

Abstract: A microelectromechanical systems (MEMS) device includes at least two rate sensors (20, 50) suspended above a substrate (30), and configured to oscillate parallel to a surface (40) of the substrate (30). Drive elements (156, 158) in communication with at least one of the rate sensors (20, 50) provide a drive signal (168) exhibiting a drive frequency. One or more coupling spring structures (80, 92, 104, 120) interconnect the rate sensors (20, 50). The coupling spring structures enable oscillation of the rate sensors (20, 50) in a drive direction dictated by the coupling spring structures. The drive direction for the rate sensors (20) is a rotational drive direction (43) associated with a first axis (28), and the drive direction for the rate sensors (50) is a translational drive direction (64) associated with a second axis (24, 26) that is perpendicular to the first axis (28).