Abstract: Microelectronic packages and methods for producing microelectronic packages are provided. In one embodiment, the method includes bonding a first Microelectromechanical Systems (MEMS) die having a first MEMS transducer structure thereon to a cap piece. The first MEMS die and cap piece are bonded such that a first hermetically-sealed cavity is formed enclosing the first MEMS transducer. A second MEMS die having a second MEMS transducer structure thereon is further bonded to one of the cap piece and the second MEMS die. The second MEMS die and the cap piece are bonded such that a second hermetically-sealed cavity is formed enclosing the second MEMS transducer. The second hermetically-sealed cavity contains a different internal pressure than does the first hermetically-sealed cavity.

Abstract: A proportional-to-absolute-temperature (“PTAT”) circuit includes a bias component; first, second, third, and fourth transistors; an output transistor; and a first resistive component. A first terminal of the bias component is coupled to a voltage supply node. The first and second transistors are connected to a second terminal of the bias component. The third and fourth transistors have different current densities. The first transistor is coupled to the third transistor. The second transistor is coupled to the fourth transistor. The fourth transistor and the first resistive component are coupled to a voltage common node. The output transistor has a control terminal coupled to the second and fourth transistors, a first current terminal connected to an output node, and a second current terminal coupled to the third transistor and the first resistive component. The PTAT circuit is configured to generate at least a portion of a PTAT current at the output node.

Abstract: A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.

Abstract: A method and apparatus are provided for computing a CRC value for a packet containing a data stream with a modified data unit data and one or more additional data units extending to the end of the data stream by computing a first CRC value from the one or more additional data units, computing a second CRC value from the modified data unit, adjusting the second CRC value based on a shift length equal to a distance of the one or more additional data units to compute a perspective shifted second CRC value by using fixed number of distance lookup table operations, and generating an updated CRC value from the first CRC value and perspective shifted second CRC value, thereby avoiding recalculating a complete CRC value based on an entirety of the modified data stream.

Abstract: In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. The semiconductor package includes a phase advance network connected to the first output matching network. The phase advance network is configured to offset at least a portion of the phase delay of the first output matching network. The semiconductor package includes a peaking amplifier connected to a second output of the power divider and the output combining node, and a second output matching network connected to the peaking amplifier.

Abstract: A device simulation system performs a set of tests by applying, for each test in the set, a corresponding test stimulus to a simulation of the electronic device. In response to each test stimulus, the simulation generates corresponding output information which the device simulation system compares to a specified expected outcome to identify a test result for that test stimulus. In addition, for each test stimulus, the device simulation system generates test coverage information indicating the particular configuration of the simulated electronic device that resulted from the stimulus. The device simulation system correlates the coverage information with the test results to identify correlation rules that indicate potential relationships between test results and configurations of the simulated device.

Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

Abstract: A pulse wave shaper for reducing the radiation emission level is disclosed. The pulse wave shaper, comprises a first integrator, wherein the first integrator receives a first pulse wave and generates a second pulse wave and a second integrator coupled to the first integrator, wherein the second integrator receives the second pulse wave and generates a third pulse wave with a pulse wave amplitude. The first pulse wave comprises a first pulse wave shape, the second pulse wave comprises a second pulse wave shape, and the third pulse wave comprises a third pulse wave shape. The third pulse wave shape, when transmitted over a bus, generates a reduced radiation emission level.

Abstract: An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.

Abstract: By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via layer that includes a top surface and a bottom surface; a plurality of vias within the via layer, wherein the plurality of vias extend from the bottom surface to the top surface; a first via of the plurality of vias extending from the bottom surface to the top surface at a first angle; and a second via of the plurality of vias extending from the bottom surface to the top surface at a second angle.

Abstract: In a system on chip (SOC) device, continuity of a memory repair signature chain, which is accessible by all enabled memory systems, is provided, even when certain memory systems are gated (off) for certain SOC configurations. A mechanism for converting between compressed and uncompressed memory repair data within the repair chain is provided so that memory systems that support either uncompressed memory repair data (such as ternary content addressable memories) or compressed memory repair data can be incorporated in the SOC.

Abstract: A method and apparatus for electric motor thermal management is provided. A thermal model allows estimation of temperatures of an electric motor and determination of a motor overload condition. The thermal model is based on electrical parameters that can be measured in a motor control circuit. An electric motor control method and circuit utilizes a back electromotive force (EMF) measurement circuit, a processor coupled to the back EMF measurement circuit for receiving a back EMF measurement and for calculating a thermal model of the electric motor, the thermal model based on a stator-to-ambient thermal resistance value accounting for a sum of a stator-to-case thermal resistance and a case-to-ambient thermal resistance, and an electric motor driver circuit coupled to the processor for providing drive signals for controlling delivery of power to the electric motor based on the thermal model of the electric motor.

Abstract: A network having a plurality of switch points, each switch point having both a main multi-stage pipeline and a look-ahead pipeline between input ports and output ports of the plurality of switch points is described. The look-ahead pipeline has fewer pipeline stages than the main multi-stage pipeline. Look-ahead information and corresponding packet are received at an input port. A first stage look-ahead request is generated from the look-ahead information. A second stage look-ahead request is generated in response to the first stage look-ahead request being not granted. And in response to the second stage look-ahead request being granted, transmitting a packet through the switch point using the look-ahead pipeline.

Abstract: A statistical power indication monitor including a random pattern generator that generates random sample assertions of a sample signal, a total counter that counts a total number of the random sample assertions within a sample time interval, detect logic that provides a detection signal for each power indication signal that is asserted coincident with the sample signal, and counter logic that counts a number of assertions of each detection signal during the sample time interval. The assertion count of each power indication signal divided by the total count provides a statistical indication of power consumption of a corresponding system. A user may use the statistical monitoring information to adjust system or application operation. The random pattern generator may be a pseudo-random pattern generator including a linear feedback shift register and may have programmable seed and sample rate.

Abstract: A program trace data compression mechanism in which execution of a variable length execution set (VLES) including multiple non-branch conditional instructions are traced in real-time in a manner that allows the instruction execution to be reconstructed completely by correlating the trace data with the traced binary code.

Abstract: An integrated circuit, such as for example an application specific integrated circuit, as well as a method of testing such a circuit, are disclosed herein. In one example embodiment, the integrated circuit includes a plurality of pins including a power pin, a ground pin, and a first communication pin, a test mode circuit, and a communication circuit. The integrated circuit additionally includes a first switch connected to the first communication pin, where the first switch is configured to couple the first communication pin to either the test mode circuit or the communication circuit. The integrated circuit further includes a control circuit coupled to the first switch and configured to control whether the first switch is operated to couple the first communication pin to the test mode circuit or to the communication circuit based upon or in response to an operating mode.

Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.

Abstract: A method for debugging a computer program is proposed. The method includes a step of running at least part of the computer program on a computer, thereby prompting the computer to execute a sequence of instructions and to generate a trace corresponding to the executed sequence of instructions. When the program has generated an exception, selecting a set of one or more exception strings on the basis of the trace, so that each of the exception strings is a unique substring of the trace. The exception strings are indicated to a user or to a debugging tool. The set of exception strings may notably include the ultimate shortest unique substring of the trace. A computer program product is also described.

Abstract: A pressure sensor (20) includes a test cell (32) and sense cell (34). The sense cell (34) includes an electrode (42) formed on a substrate (30) and a sense diaphragm (68) spaced apart from the electrode (42) to produce a sense cavity (64). The test cell (32) includes an electrode (40) formed on the substrate (30) and a test diaphragm (70) spaced apart from the electrode (40) to produce a test cavity (66). Both of the cells (32, 34) are sensitive to pressure (36). However, a critical dimension (76) of the sense diaphragm (68) is less than a critical dimension (80) of the test diaphragm (70) so that the test cell (32) has greater sensitivity (142) to pressure (36) than the sense cell (34). Parameters (100) measured at the test cell (32) are utilized to estimate a sensitivity (138) of the sense cell (34).