Patents Assigned to Freescale
  • Phase-locked loop with frequency bounding circuit
    Patent number: 9490824
    Abstract: A phase-locked loop (PLL) for generating an oscillating signal includes a frequency bounding circuit. When a frequency of the oscillating signal is greater than a first threshold value, which is greater than a maximum normal operational frequency of the PLL, the frequency bounding circuit forces a charge pump to discharge a loop filter until the oscillating signal frequency is less than a second threshold value that is within the normal operational frequency range of the PLL. When the frequency of the oscillating signal is less than a third threshold value, which is less than a minimum normal operational frequency of the PLL, the frequency bounding circuit forces the charge pump to charge the loop filter until the oscillating signal frequency is greater than a fourth threshold value that is within the normal operational frequency range of the PLL.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Devesh P. Singh, Firas N. Abughazaleh, Anand Kumar Sinha, Sanjay K. Wadhwa
  • Method and device implementing execute-only memory protection
    Patent number: 9489316
    Abstract: Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, David J. Schimke
  • System for monitoring and controlling the power of a radio frequency (RF) signal in a short-range RF transmitter
    Patent number: 9491723
    Abstract: A system for monitoring and controlling the power of a Radio Frequency (RF) signal in a short-range RF transmitter. An RF signal-generation unit generates the RF signal. A power amplifier amplifies the RF signal. An impedance-matching network matches the output impedance of the power amplifier to input impedance of an antenna. One or more RF power monitors monitor the voltage amplitude of the RF signal at the output of at least one of the RF signal-generation unit, the power amplifier and the impedance-matching network. The one or more RF power monitors further generate at least one alarm signal, based on the voltage amplitude of the RF signal. A control unit modifies at least one operating parameter of at least one of the RF signal-generation unit and the power amplifier, based on the at least one alarm signal generated by the one or more RF power monitors.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Alain Huot, Christophe Pinatel
  • Pulse width modulation with effective high duty resolution
    Patent number: 9490792
    Abstract: A pulse width modulation (PWM) signal generator generates a PWM signal having a specified effective PWM duty resolution for a corresponding cycle window. The PWM signal generator receives an N-bit value representing a duty to be implemented and sets values X and Y to the M least significant bits and the N-M most significant bits, respectively, of the N-bit value. The value M can be determined based on the value N and a maximum implementable frequency of a clock signal used to time the generation of each PWM cycle. The PWM signal generator generates a cycle window of 2M PWM cycles, each PWM cycle of the cycle window having a duty of either Y or Y+1. The number of PWM cycles in the cycle window having the duty Y+1 is based on the value X and the PWM cycles having a particular duty are contiguous within the cycle window.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Bin Zhao
  • Self-bootstrap driving circuit and DC-DC converter
    Patent number: 9490697
    Abstract: A self-bootstrap driving circuit includes a first input receiving a first control signal; an output, to which a load having an electro-inductive component may be connected; a power switch having first and second current terminals and a control terminal, and being arranged to drive power from a power supply terminal to the load; a bootstrap circuitry arranged to drive the control terminal of the power switch based on the control signal; and a current path between the electro-inductive component of the load and the control terminal of the switch, said current path being arranged to provide direct transfer from said electro-inductive component to said control terminal of the switch of an overvoltage generated at the electro-inductive component to provide an overdrive voltage to said control terminal of the switch.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: November 8, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Eric Rolland
  • System for alignment of RF signals
    Patent number: 9491758
    Abstract: A radio-frequency (RF) transceiver for aligning a time offset (TO) of RF signals transmitted to the RF transceiver by a user equipment (UE) includes first and second processors and first and second system memories. The first processor provides values of a cool-off period, a reset interval, a filter period, a first filter, and a primary threshold to the second processor. The second processor generates a second filter value, first and second threshold values, an instantaneous TO value, and a TO value. The second processor transmits a default TO value and a modified TO value as the TO value to the first processor during first and second time periods, respectively. The first processor generates a control signal based on the TO value. The second processor transmits the modified TO value to the UE based on the control signal.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ajay Sharma, Gopikrishna Charipadi, Loksiva Paruchuri
  • Phase shift and attenuation circuits for use with multiple-path amplifiers
    Patent number: 9490755
    Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Abdulrhman M. S. Ahmed, Mario M. Bokatius, Paul R. Hart, Joseph Staudinger, Richard E. Sweeney
  • Glitch-free clock switching circuit using Muller C-elements
    Patent number: 9490789
    Abstract: A clock switching circuit includes first and second clock lines, first and second selection lines, and first through fourth Muller C-elements. The Muller C-elements are connected to the clock and selection lines and first and second logic gates. First and second delay cells are connected to the clock lines and the second and fourth Muller C-elements. A first AND gate is connected to the first clock line, the first Muller C-element, and the first delay cell. A second AND gate is connected to the second delay cell, the third Muller C-element, and the second clock line, and an OR gate is connected to the first and second AND gates.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chaoxuan Tian, Zhihong Cheng, Zhiling Sui
  • Programmable synchronous clock divider
    Patent number: 9490777
    Abstract: A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Inayat Ali, Puneet Dodeja, Sachin Jain
  • Semiconductor device comprising an ESD protection device, an ESD protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device
    Patent number: 9490243
    Abstract: A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: November 8, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean Philippe Laine, Patrice Besse
  • High-speed address fault detection using split address ROM
    Patent number: 9490031
    Abstract: High-speed address fault detection is described that uses a split address ROM (read only memory) for address fault detection in split array memory systems. In one aspect, a disclosed embodiment includes separate arrays of memory cells having a plurality of wordlines and being configured to be accessed based upon a wordline address. Two or more separate address ROMs are also provided with each address ROM being associated with a different one of the separate arrays and being configured to provide outputs based upon only a portion of the wordline address. Detection logic is coupled to the outputs from the address ROMs and is configured to provide one or more fault indicator outputs to indicate whether an address fault associated with the wordline address has occurred. The outputs form the address ROMs can also be used for wordline continuity fault detection. Other embodiments are also described.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Scott I. Remington
  • Semiconductor device with enhanced 3D resurf
    Patent number: 9490322
    Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Hongning Yang, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Display controller for display panel
    Patent number: 9484004
    Abstract: A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: November 1, 2016
    Assignee: FREESCALE SEMIOCNDUCTOR, INC.
    Inventors: Chanpreet Singh, Kshitij Bajaj, Nakul Grover, Michael A. Staudenmaier
  • Phase locked loop having fractional VCO modulation
    Patent number: 9484936
    Abstract: An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: November 1, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Khurram Waheed, Kevin B. Traylor
  • Interface system and method
    Patent number: 9483209
    Abstract: An interface system has a first media access controller having a first MAC buffer for storing at least one first-type frame in a first frame format according to a first communication protocol. A time synchronization module is arranged to, upon detecting the start of the first-type frame, determine a first timestamp from a master clock signal and latch the first timestamp into a first timestamp register. A processor is arranged to: retrieve the first timestamp from the first timestamp register, and transfer a first-type frame between the first MAC buffer and a first local memory in a block-wise manner as a plurality of blocks. The processor is arranged to process the plurality of blocks of the first-type frame using the first timestamp as retrieved from the first timestamp register.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 1, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Graham Edmiston, Heinz Klaus Richard Wrobel
  • Voltage level shifter module
    Patent number: 9484922
    Abstract: A voltage level shifter module comprising at least one input arranged to receive an input signal, and at least one cascode transistor arranged to receive at a gate thereof at least one reference voltage signal. The voltage level shifter module further comprises at least one reference voltage control component arranged to detect logical state transitions within the input signal from at least a first logical state to a second logical state, and cause the reference voltage signal applied to the gate of the at least one cascode transistor to be pulled down to a reduced voltage upon detection of a logical state transition within the input signal from at least a first logical state to a second logical state.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: November 1, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Andrey Evgenevich Malkov
  • Voltage sampling switch and method therefor
    Patent number: 9484905
    Abstract: A voltage switch for handling negative voltages includes an input terminal coupled to a voltage that is greater than a voltage rating of oxide in the voltage switch, a top capacitor plate pre-charge module including three cascoded p-channel transistors coupled between a supply voltage and a top plate of a capacitor, a bottom capacitor plate pre-charge module including two cascoded n-channel transistors coupled between a bottom plate of the capacitor and ground, and an output voltage module including an output terminal and four cascoded n-channel transistors with control electrodes of a first and fourth of the cascoded n-channel transistors coupled to a boost node. Control electrodes of a second and third of the cascoded n-channel transistors coupled to the top plate of the capacitor. A voltage switch for positive voltages is also disclosed.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: November 1, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Khoi B. Mai, Jon S. Choy, Michael T. Berens
  • Semiconductor devices, semiconductor device packages, and packaging techniques for impedance matching and/or low frequency terminations
    Patent number: 9484222
    Abstract: A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 1, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Hussain H. Ladhani, Lu Li, Mahesh K. Shah, Lakshminarayan Viswanathan, Michael E. Watts
  • Semiconductor device with heat spreader
    Patent number: 9484289
    Abstract: A semiconductor device includes a package body, a semiconductor die embedded in the package body and a heat spreader attached to a top surface of the package body and spaced from semiconductor die. The heat spreader may be formed of solder that is melted within a recess in the top surface of the package body.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: November 1, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: You Ge, Meng Kong Lye, Penglin Mei
  • Systems and methods for managing return stacks in a multi-threaded data processing system
    Patent number: 9483272
    Abstract: A processor is configured to execute instructions of a first thread and a second thread. A first return stack corresponds to the first thread, and a second return stack to the second thread. Control circuitry pushes a return address to the first return stack in response to a branch to subroutine instruction in the first thread. If the first return stack is full and borrowing is not enabled by the borrow enable indicator, the control circuitry removes an oldest return address from the first return stack and not store the removed oldest return address in the second return stack. If the first return stack is full and borrowing is enabled by the borrow enable indicator and the second thread is not enabled, the control circuitry removes the oldest return address from the first return stack and push the removed oldest return address onto the second return stack.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: November 1, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jeffrey W. Scott, William C. Moyer, Alistair P. Robertson