Abstract: There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilized as an electrical connection to a metal layer of the MIM stack.

Abstract: A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are formed of conductive material that extend through the first IC die from an outer surface on a first side of the die to an outer surface of a second side of the die. The package further includes first electrical connections contacting the first side of the first IC die, and second electrical connections contacting the second side of the first IC die. The first electrical connections are independent of the second electrical connections. Molding compound encapsulates the first IC die and the first and second electrical connections. The semiconductor package is mounted on a substrate so that the first and second sides of the IC die are oriented perpendicular to the substrate.

Abstract: An integrated circuit comprising voltage modulation circuitry arranged to convert an input voltage level at an input node to an output voltage level at an output node. The voltage modulation circuitry comprises a switching element arranged to connect the input node to the output node when in an ON condition, and switching control module operably coupled to the switching element and arranged to control the connection of the input node to the output node by the switching element in accordance with a switching frequency. The voltage modulation circuitry further comprises frequency control module operably coupled to the switching control module and arranged to receive an indication of the input voltage level at the input node, and to configure the switching frequency based at least partly on the input voltage level indication.

Abstract: A Universal Serial Bus (USB) controller includes a USB transceiver to detect a high-speed (HS) disconnect between the USB controller and a device connected to it. The USB transceiver includes a reference-voltage generation circuit, a HS current driver, first and second comparators, and a multiplexer. The reference-voltage generation circuit generates HS disconnect and transmitter reference-voltage signals that have a constant voltage difference. The first comparator receives DP and DM signals that correspond to a HS Start of Frame (SOF) packet during HS disconnect detection, and generates a control voltage. The multiplexer outputs at least one of the DP and DM signals based on the logic state of the control voltage. The second comparator receives the selected signal and the HS disconnect reference-voltage signal, and outputs a HS disconnect output voltage signal when the selected signal is greater than the HS disconnect reference-voltage signal.

Abstract: A debug configuration tool for configuration of on-chip debug features comprises a database comprising predefined analysis points, each relating to a configurable chip entity, and comprising a configurable condition and a configurable action for the chip entity, a plurality of predefined analysis groups, each relating to a group of configurable chip entities, and comprising a configurable condition and a configurable action for the group of chip entities. The tool comprises a graphical user interface module arranged to display representations of at least some of the analysis points and the analysis groups on different levels of detail, and to receive input from a user to set the configurable conditions and/or actions for the displayed analysis points and the analysis groups. An application program interface module processes data received from the graphical user interface module to obtain debug settings and to communicate the debug settings to a debug target system configuration module.

Abstract: A display controller comprising a blending stage and a blending controller. The blending stage is provided for blending multiple image layers into one display output image and comprises a plurality of input channels for receiving pixel data for the multiple image layers. The blending stage further comprises multiple blenders for combining the pixel data received by at least two input channels of the plurality of input channels. The blending controller is coupled to the blending stage for controlling operation of the blending stage. The blending stage further comprises a controllable switch for coupling an output of at least one blender of the multiple blenders to a display output of the blending stage for regular on-the-fly blending or to an offline blending memory for storing a result of an offline blending task.

Abstract: A method of and apparatus for fault detection utilizing a diagnostic procedure by a diagnostic device to detect a short circuit between at least two of a plurality of load electrical connections, the diagnostic procedure comprising applying a test electrical signal to each of the load electrical connections in turn and while applying the test electrical signal to a first one of the load electrical connections, detecting whether an electrical output is present, in response, on any other of the load electrical connections, wherein the detecting by the diagnostic device includes applying the test electrical signal to the first one of the load electrical connections in an operational mode of the apparatus when an electrically controlled switch connected to the first one of the load electrical connections is in an off state.

Abstract: A method of data streaming in a streaming system (200) that comprises a processor (202) and a controller (204) operably coupled to a streaming peripheral (214) via a shared interconnect (206) is described. The method comprises at the controller, receiving at least one descriptor that points to at least one header data element in memory and at least one payload buffer element in the streaming peripheral (214); reading the at least one descriptor (211) by the controller (204); fetching by the controller the at least one header data element from memory and the at least one payload element from the payload buffer (212) in the streaming peripheral (214) referred to by the descriptor (211).

Abstract: A Low-Voltage Differential Signaling (differential signaling) driver circuit (10) comprising enable circuitry for enabling and disabling the differential signaling driver circuit (10) in accordance with an control signal is described. The differential signaling driver circuit (10) comprises: a differential output (12, 13) connected or connectable to a differential signaling receiver circuit via a differential transmission line; current control circuitry (14) for driving a signal current through the differential output (12, 13) in accordance with a driver signal; feedback circuitry (16) for driving the current control circuitry (14) to counteract a difference between a common mode voltage of the differential output (12, 13) and a reference voltage from a reference voltage provider; and the enable circuitry (18).

Abstract: A video processing system dynamically adjusts video processing prediction error reduction computations in accordance with the amount of motion represented in a set of image data and/or available memory resources to store compressed video data. In at least one embodiment, video processing system adjusts utilization of prediction error computational resources based on the size of a prediction error between a first set of image data, such as current set of image data being processed, and a reference set of image data relative to an amount of motion in a current set of image data. Additionally, in at least one embodiment, the video processing adjusts utilization of prediction error computation resources based upon a fullness level of a data buffer relative to the amount of motion in the current set of image data.

Abstract: A method and apparatus are provided for classifying received network frames (106) by using a key composition rule (134) having a header portion (NF) and multiple variable length key extract commands in a coded order sequence to sequentially generate multiple data fields (FIELD 1-FIELD n) using operands contained in the key extract commands to generate a lookup key (116) by combining multiple data fields in the same coded order sequence as the key extract commands.

Abstract: And FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data.

Abstract: A digital front end channelization device for one or more carrier signals comprises a per carrier section and a composite section. The composite section may include signal processing units, each of which may include an inverse Fourier transform unit for transforming a composite carrier signal into a time domain signal, a sample detection and selection unit for detecting and selecting a peak of the time domain signal, a clipping unit for clipping the time domain composite carrier signal to produce an error signal, a Fourier transform unit, for transforming the error signal into a frequency domain error signal, a frequency shaping unit for frequency shaping the frequency domain error signal, a summation unit for subtracting the frequency shaped frequency domain error signal from the composite carrier signal, and a phase selection unit for phase adjustment of the resulting signal.

Abstract: A technique for frame synchronization in a communication system includes performing symbol correlation on received signal samples. A determination is made as to whether a magnitude of the symbol correlation is greater than a first threshold. In response to the magnitude of the symbol correlation being greater than the first threshold, an indication is provided that the received symbol is a valid symbol (e.g., a SYNCP symbol or SYNCM symbol). In response to the magnitude of the symbol correlation being less than the first threshold, an indication is provided that the received symbol is an indeterminate symbol (e.g., an invalid symbol or a SYNCM/2 symbol).

Abstract: An embedded software debug system with partial hardware acceleration includes a computer that executes a debug software stack. The debug software stack includes high level operations. The system also includes a remote microcontroller electronically connected to the computer. The system further includes an embedded processor electronically connected to the remote microcontroller. The remote microcontroller receives an applet from the computer and executes the applet in conjunction with the computer executing the debug software stack to debug the embedded processor. The applet includes low level protocol operations including performance critical tight-loops precompiled into machine code. The debug software stack may include a stub that replaces the tight-loops of the applet. The computer may send the applet to the remote microcontroller in response to executing the stub.

Abstract: The invention relates to a buffer circuit for a receiver device including a transconductance stage and an output stage coupled in parallel to output stages of other channels of the device. The output of the transconductance stage is connected to a base of a bipolar transistor in the output stage. A switch is connected between the base of the bipolar transistor and the emitter of the bipolar transistor. A controller is arranged to switch the buffer circuit from a switch-off mode to a switch-on mode and back. In switch-off mode the switch is switched on, so as to connect the base and the emitter of the bipolar transistor.

Abstract: A device includes a semiconductor substrate, a channel region in the semiconductor substrate having a first conductivity type, and a composite drift region in the semiconductor substrate, having a second conductivity type. The composite drift region includes a first drift region and a second drift region spaced from the channel region by the first drift region. The device further includes a drain region in the semiconductor substrate, spaced from the channel region by the composite drain region, and having the second conductivity type. The first drift region has a dopant concentration profile with a first concentration level where adjacent the channel region and a second concentration level where adjacent the second drift region, the first concentration level being higher than the second concentration level. In some embodiments, the first and second drift regions are stacked vertically, with the first drift region being shallower than the second drift region.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode material overlying a semiconductor substrate, forming a layer of masking material overlying the gate electrode material, and patterning the layer of masking material to define a channel region within a well region in the semiconductor substrate that underlies the gate electrode material. Prior to removing the patterned layer of masking material, the fabrication process etches the layer of gate electrode material to form a gate structure overlying the channel region using the patterned layer of masking material as an etch mask and forms extension regions in the well region using the patterned layer of masking material as an implant mask. Thereafter, the patterned layer of masking material is removed after forming the gate structure and the extension regions.

Abstract: A pressure sensor has a housing having a bottom surface and side walls that form a cavity. A pressure sensor die is attached to the bottom of the cavity and covered with a layer of low modulus gel. A lid is secured to upper ends of the side walls and covers the cavity, gel and pressure sensor die. The lid has an inner surface facing the gel and an exposed outer surface, and includes protrusions extending from the inner surface along the side walls and towards the gel such that the gel near the upper ends of the side walls is displaced towards a central region of the cavity to ensure that the gel completely covers the pressure sensor die.

Abstract: A method for repairing a memory includes executing an Error Correction Code (ECC) for a page of the memory. The page includes a plurality of bits having an inherent number of failed bits equal to or greater than zero. The ECC is configured to correct a correctable number of failed bits from the plurality of bits. A location of a failure prone bit in the page is determined from a cache in response to the correctable number of failed bits being less than the inherent number of failed bits. A state of the failure prone bit is changed to a new state in response to determining the location of the failure prone bit. The ECC is executed in response to the state of the failure prone bit being changed to the new state.