Abstract: The invention relates to a thin film transistor memory and its fabricating method, This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulting layer and the second layer metal nanocrystals grown by ALD method. in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown. by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method.

Abstract: This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates.

Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.

Abstract: The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree.

Abstract: The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning and passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.

Abstract: An effective fraction from the fruiting bodies of Ganoderma lucidum, extraction method, use and preparation thereof are provided. The effective fraction is prepared from the defatted fruiting bodies of Ganoderma lucidum by extracting with alkali, dialyzing and drying. The effective fraction has effect of significantly lowering blood sugar.

Abstract: The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer.

Abstract: A self-directed and self-assembled nanomedicine of quantized conductive junction and its preparation process are introduced. In the present disclosure, bio-organic medicine proteins are prepared into a quantized conductive junction with a nanostructure quantum dot and a polymer monolayer on an inorganic silicon surface by seven cooperative modes; and the preparation process of this inorganic-organic-biological hetero-polymer nano-structure component with free radical electrons, aromatic hetercycle structures, bio-fluorescence, and redox bioactivity is consist of making unitary, binary, ternary, and/or quaternary liquid biochemical medicines ingredients of an antioxidase antioxidant, a ?-adrenergic receptor agonist, a P2-purinergic receptor agonist, and/or a phenylalkylamine calcium channel blocker into a solid state quantized conductance junctions using L16(2)15 and L9(3)4 orthogonal protocol.

Abstract: This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and the device is of a simple gate-control pn junction structure; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The quantity of charges in the floating gate determines the device threshold voltage, thus realizing the memory functions. This invention features capacity of manufacturing memory devices able to reduce the chip power consumption through advantages of high driving current and small sub threshold swing, is applicable to semiconductor memory devices manufacturing based on flexible substrates and flat panel displays and floating gate memories, etc.

Abstract: The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly.

Abstract: The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for manufacturing a copper-diffusion barrier layer. In the present invention, a proper reaction precursor has been selected and the atomic layer deposition (ALD) technology has been adopted to develop Co or Ru on a TaN layer to obtain a diffusion barrier layer used in the interconnection for process nodes no more than 32 nm, which overcomes the insufficiency of the PVD deposition Ta/TaN double-layer structure as the copper-diffusion barrier layer in step coverage and conformity, and also effectively solves various serious problems in the Cu/low-k dual damascene process, such as the generation of voids in grooves and through-holes, and electromigration stability.

Abstract: The invention provides a dual-mode voltage-controlled oscillator (DMVCO), a frequency synthesizer and a wireless receiving device, and pertains to the technical field of integrated circuit of radio frequency wireless receiver. The DMVCO and the frequency synthesizer can operate in a wideband mode and a quadrature mode. When operating in the quadrature mode, a quadrature signal is provided for a Single Sideband Mixer of the frequency synthesizer by a quadrature coupling of a first voltage-controlled oscillator unit and a second voltage-controlled oscillator unit in the DMVCO in the overlapped frequency band so that the frequency synthesizer can cover a higher output frequency band. Therefore, the tuning range of the DMVCO of the invention is wide, and the frequency synthesizer using the DMVCO is low in power consumption, simple in structure and has good frequency spur performance.

Abstract: A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance.

Abstract: The present invention belongs to the technical field of memory storage and specially relates to a NiO-based resistive random access memory system (RRAM) and a preparation method thereof. The RRAM is comprised of a substrate and a metal-insulator-metal (MIM) structure, wherein the electrodes are metal films, such as copper, aluminum, etc., capable of being applied to the interconnection process, and the resistive switching insulator is an Al2O3/NiO/Al2O3 laminated dielectric film. The MIM structure in the invention shows stable switching between the bi-stable resistance states as well as memory features; compared with the RRAM that only uses a single NiO-based dielectric film, the storage window is increased, and the resistance stability is improved. Therefore, the NiO-based RRAM has a good prospect in actual application. The present invention further provides a method for preparing the abovementioned memory storage system.

Abstract: Preparation of oxidation-reduction (redox) nano-medicine quantum dot room temperature superconductor quantum bit (qubit) networks includes processes of making unitary, binary, ternary, an d/or quaternary liquid pharmaceutical ingredients of an antioxidase antioxidant, a ?-adrenergic receptor agonist, a P2-purinergic receptor agonist, and/or a phenylalkylamine calcium channel blocker in combination with either 1:20 xanthine oxidase (XO):xanthine (X) or X alone in a liquid phase by using the L16(2)15 and L9(3)4 orthogonal optimization design protocols and modulating spatial distance constraint from about 0.1 ? to about 200 ? as well as a 10 class clean bottom-up self-assembly approach.

Abstract: The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well.

Abstract: Provided herein are methods and compositions for the diagnosis, prognosis and treatment of Hepatocellular carcinoma (HCC). Also provided are methods of identifying anti-HCC agents.

Abstract: The present invention belongs to the technical field of semiconductor devices, and more specifically, relates to a gate-controlled PN field-effect transistor and the control method thereof The gate-controlled PN field-effect transistor disclosed by the present invention comprises a semiconductor substrate region, a drain region and a source region on the left and right sides of the substrate region, and gate regions on the upper and lower sides of the substrate region. The gate-controlled PN field-effect transistor works in the positive bias state of the source-drain PN junction and is conducted from the middle of the substrate region. The gate-controlled PN field-effect transistor provided by the present invention decreases the leakage current and increases the drive current at the same time, namely decreases the chip power consumption and improves the chip performances at the same time.

Abstract: The present invention provides long half life genetically modified TFPI sequences (LTFPI) for anticoagulation. On the genetically modified TFPI sequence, the lysine at the carboxy-terminal sites 241, 254, 260 and 261 are replaced by alanin and the amino acid asparagine at glycosylation sites 117, 167, 228 and the amino acids serine and threonine at glycosylation sites 174 and 175 are substitutionally mutated. The present invention also provides methods of making the LTFPI through high efficient LTFPI expression from yeast production system.

Abstract: A system for detecting single-shot pulse contrast includes a correlator generating a correlation signal, a spectral filter filtering light signals having wavelengths different from the correlation signal, a fiber array comprising a plurality of fibers with different lengths for transmitting the correlation signal in parallel forming parallel correlation signals, and a fiber bundle bounding the fibers at the end thereof for converging the parallel correlation signals, wherein due to different lengths of the fibers, the parallel correlation signals are converted into serial correlation signals at end of the fibers, a plurality of fiber attenuators spliced into at least one of the fibers respectively for attenuating the parallel correlation signals, a detector for detecting the serial correlation signals to produce analog signals, an A/D convertor converting the analog signals to digital signals, and a computer for processing the digital signals for retrieving the single-shot pulse contrast.