Abstract: A method for diminishing the signal interference of a transmission path of an optical fibre interference system, belonging to the technical field of optical fibre sensing. A wavelength division multiplexer (19) is connected in series to the end of an induced optical fibre, a wavelength component (?2) is separated from an operating path by means of the wavelength division multiplexer (19) so as to measure a signal picked up by a transmission path, and the signal is removed from overall interference sensing signals by taking same as a reference, thereby obtaining a target measurement signal. Also provided is a structure for diminishing the signal interference of a transmission path of an optical fibre interference system. The method and the structure are simple; moreover, the device connected to the end of an induced optical fibre is passive, so that power supply is not required, and it is easy to implement.

Abstract: A method using wavelength division multiplexing for reducing the light diffusion and light reflection interference in an interference path, comprising: connecting a wavelength division multiplexer (10) serially at the end of a sensing optical fiber (6); using the wavelength division multiplexer (10) to extract a wavelength component from a working path for measuring the interfering signal caused by light diffusion and light reflection; using the signal as a reference, extracting the effective signal component that has been interfered with by light diffusion and light reflection, and obtaining a pure effective signal. Because the device connected at the end of the sensing optical fiber (6) is passive and requires no power, the system is easy to implement and is particularly suitable for situations in which power provision is difficult at the end of the sensing optical fiber (6). The method is suitable for long distance pipeline monitoring and wide-range optical fiber perimeter security.

Abstract: The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor forms a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps.

Abstract: A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (fT) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (fmax). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.

Abstract: The present invention relates to a ferroelectric analyzing device and a method for adjusting ferroelectric domain switching speed with the ferroelectric analyzing device, and pertains to the technical field of characteristic test of solid-state dielectrics. The ferroelectric analyzing device comprises a voltage pulse generator for generating square pulse signal, which is biased on a ferroelectric thin film so as to switch the polarization of ferroelectric domains, the ferroelectric analyzing device further comprises a variable resistor which is connected in series with the ferroelectric thin film. The variable resistor is used for adjusting domain switching current so as to realize adjustment of domain switching speed of ferroelectric domains. In the method, the square pulse signal is biased on the ferroelectric thin film, and an adjustment of domain switching speed of ferroelectric domains can be realized by adjusting the resistance value of the variable resistor.

Abstract: The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips.

Abstract: The invention belongs to the technical field of organic chemistry, in particular being a method for preparing (+)-tricyclic hydroxyl lactone. The preparation of the (+)-tricyclic hydroxyl lactone compound in the prior art has lengthy steps, low stereoselectivity and high costs. The (+)-tricyclic hydroxyl lactone of the invention is obtained by an asymmetric oxidation reaction of prochiral tricyclic lactones in an organic solvent with an optically active Davis oxidant in the presence of an organic base. The method of the invention uses easily available raw materials, has low costs, good selectivity, and is suitable for large-scale preparation.

Abstract: The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi3, CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.

Abstract: It is disclosed herein that expression of microRNA-26 is decreased in hepatocellular (HCC) tumor tissue relative to non-cancerous tissue, and that a low level of microRNA-26 is associated with a poor clinical outcome. It is also disclosed herein that a low expression level of microRNA-26 is correlated with a favorable response to interferon (IFN)-? therapy in HCC patients. Thus, provided herein is a method of predicting the clinical outcome of a patient diagnosed with HCC comprising detecting the level of microRNA-26 expression in a sample obtained from the patient. Also provided is a method of selecting a patient diagnosed with HCC as a candidate for IFN-? therapy, comprising detecting the level of microRNA-26 expression in a sample obtained from the patient. A method of identifying therapeutic agents for the treatment of HCC, comprising screening candidate agents in vitro to select an agent that increases expression of microRNA-26 in HCC cells are also provided.

Abstract: This invention belongs to the technical field of memories and specifically relates to a resistive random access memory structure with an electric-field strengthened layer and a manufacturing method thereof. The resistive random access memory in the present invention can include a top electrode, a bottom electrode and a composite layer which is placed between the top electrode and the bottom electrode and have a first resistive switching layer and a second resistive switching and electric-field strengthened layer; the second resistive switching and electric-field strengthened layer cab be adjacent to the first resistive switching layer and have a dielectric constant lower than that of the first resistive switching layer. The electric-field distribution in the RRAM unit is adjustable.

Abstract: The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors.

Abstract: The present invention relates compositions and methods for microRNA (miRNA) expression profiling of colorectal cancer. In particular, the invention relates to a diagnostic kit of molecular markers for identifying one or more mammalian target cells exhibiting or having a predisposition to develop colorectal cancer, the kit comprising a plurality of nucleic acid molecules, each nucleic acid molecule encoding a miRNA sequence, wherein one or more of the plurality of nucleic acid molecules are differentially expressed in the target cells and in one or more control cells, and wherein the one or more differentially expressed nucleic acid molecules together represent a nucleic acid expression signature that is indicative for the presence of or the predisposition to develop colorectal cancer.

Abstract: The present invention belongs to the technical field of semiconductor devices, and discloses a structure for interconnecting a medium of low dielectric constant with copper and the integration method thereof. It includes: using a combination of copper interconnections and air gaps to reduce capacity, and a special structure to support copper conductors so as to maintain the shape of copper conductors after removing the medium. The advantage of the present invention is that it can realize the complete air gap structure without short circuit or disconnection of copper conductors as well as the complete air gap structure with long conductors, thus reducing RC delay.

Abstract: The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor faults a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps.

Abstract: The present invention provides a pharmaceutical composition or a cosmetic product which can accelerate production of ceramide in cells. The ceramide production-accelerating agent contains a plant selected from the group consisting of Radix Heraclei Scabridi, Rhizoma Dioscoreae, Radix Rehmanniae, Rhizoma Atractylodis Macrocephalae, Radix Glycyrrhizae, Radix Et Rhizoma Rhei, Pseudobulbus Bletillae, Radix Polygoni Multiflori, Radix Platycodi, and Herba Leonuli, or an extract thereof as an active ingredient. Further, the present invention provides a moisturizing agent containing a plant selected from the group consisting of Herba Leonuri and Rhizoma Dioscoreae, or an extract thereof as an active ingredient.

Abstract: The present invention pertains to the technical field of one-time programmable memory (OTP), and in particular to a one-time programmable memory unit, OTP, and method of fabricating the same. The OTP unit comprises a lower electrode, an upper electrode and a storage medium layer placed between the upper electrode and the lower electrode, the storage medium layer comprises a first metal oxide layer and a second metal oxide layer, wherein an adjoining area for programming is formed between the first metal oxide layer and the second metal oxide layer. The OTP comprises a plurality of the above-described one-time programmable memory units arranged in rows and columns. The OTP unit and the OTP have such characteristics as low programming voltage, small unit area, being able to integrate into a back-end structure of integrated circuit, great process flexibility, and the method of fabricating the OTP unit and the OTP is relatively simple and low in cost.

Abstract: A single-shot pulse contrast measuring device based on non-harmonic long-wavelength sampling pulse includes a long-wavelength sampling light generation unit, a large-angle non-collinear sum-frequency cross-correlation unit and a high sensitivity signal receiving unit. The long-wavelength sampling light sum-frequency cross-correlator can allow that the beams are interacted with each other at the large non-collinear angle in the quasi-phase matching crystal, match the measuring window of the high sensitivity signal receiving system, and is in favor of eliminating the scattered light noise, thereby achieving the single measurement of the pulse contrast with large temporal window and high dynamic range. The single-shot pulse contrast measuring device of the present invention has good extensibility at the temporal window and dynamic range, and is adapted for measuring the contrast of the high-power laser with various wavelengths.

Abstract: The present invention puts forward a body-contact SOI transistor structure and method of making. The method comprises: forming a hard mask layer on the SOI; etching an opening exposing SOI bottom silicon; wet etching an SOI oxide layer through the opening; depositing a polysilicon layer at the opening followed by anisotropic dry etching; depositing an insulating dielectric layer at the opening followed by planarization; forming a gate stack structure by deposition and etching, and forming source/drain junctions of the transistor using ion implantation. By using the present invention, body contact for SOI field-effect transistors can be effectively formed, thereby eliminating floating-body effect in the SOI field-effect transistors, and improving heat dissipation capability of the SOI transistors and associated integrated circuits.

Abstract: A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (107); one drain region (108) of a first doping type; two source regions (101a, 101b) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.

Abstract: The present invention is related to microelectronic device technologies. A method for making an asymmetric source-drain field-effect transistor is disclosed. A unique asymmetric source-drain field-effect transistor structure is formed by changing ion implantation tilt angles to control the locations of doped regions formed by two ion implantation processes. The asymmetric source-drain field-effect transistor has structurally asymmetric source/drain regions, one of which is formed of a P-N junction while the other one being formed of a mixed junction, the mixed junction being a mixture of a Schottky junction and a P-N junction.