Abstract: A power conversion device including an alternating current (AC) source, a plurality of switching units connected in series between positive and negative terminals of the AC source, each including a semiconductor switching element and having a load connected thereto, each switching unit outputting, to the load connected thereto, an input current from the AC source and a direct current (DC) output voltage that is generated through ON/OFF control of the semiconductor switching elements, a capacitor connected in parallel with the AC source and with the switching units, an inductor inserted between the capacitor and the switching units, and between the AC source and the switching units, a current measurement unit that measures a value of a current flowing from the AC source to the capacitor, and a control device that performs the ON/OFF control on the semiconductor switching elements on the basis of the measured current value.
Abstract: A current detection circuit includes: a current detection unit configured to detect a potential difference between both ends of a first current detection resistor interposed between a control terminal and a drive circuit of a voltage-controlled semiconductor element including a current detection terminal; a voltage detection unit configured to detect a voltage at one of the both ends of the first current detection resistor; a voltage determination unit configured to determine whether or not a detection voltage of the voltage detection unit is not less than a threshold voltage; a voltage level adjustment unit configured to adjust a voltage level of a current detection voltage of the current detection terminal by a logical product signal of a current detection signal and a voltage determination signal; and an overcurrent detection unit configured to output an overcurrent detection signal when the adjusted current detection voltage is not less than a threshold voltage.
Abstract: A power supply system, including: a plurality of power supply apparatuses; and an acquisition unit to acquire a load parameter representing load state of the plurality of power supply apparatuses as a whole, wherein each power supply apparatus has a control unit to control, depending on the load parameter, output by said power supply apparatus according to a reference condition different from at least the other one of the plurality of power supply apparatuses, will be provided.
Abstract: Unit cells of a current sensing portion are disposed in a sensing effective region of a main non-operating region. In a sensing non-operating region of the main non-operating region excluding the sensing effective region, an n?-type region that surrounds a periphery of the sensing effective region is disposed in a surface region of the front surface of the semiconductor substrate. In the main non-operating region, a p-type base region disposed in a surface region of the front surface of the semiconductor substrate opposes the sensing effective region across the n?-type region. The p-type base region is fixed at a source potential of the main semiconductor element 11. A field insulating film on the front surface of the semiconductor substrate is thicker at a portion that covers the n?-type region that in other portions.
Abstract: A region of a portion directly beneath an OC pad is a sensing effective region where unit cells of a current sensing portion are disposed. Directly beneath the OC pad, a region surrounding a periphery of the sensing effective region is a sensing non-operating region in which no unit cells of the current sensing portion are disposed. In the sensing non-operating region, a first p-type base region that floats is provided in a surface region of the front surface of the semiconductor substrate and is separated from a second p-type base region of the sensing effective region by an n?-type region that surrounds a periphery of the sensing effective region. The n?-type region has a surface area that is greater than that of the sensing effective region. A distance between the first and the second p-type base regions is at least 0.1 ?m and is as small as possible.
Abstract: A semiconductor integrated circuit includes a high-potential-side circuit region, a high-voltage junction termination structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region via the high-voltage junction termination structure which are integrated into a single chip, and wherein a first distance between a looped well region and a buried layer in a region in which a first contact region is formed is smaller than a second distance between the looped well region and the buried layer in a region in which a carrier reception region is formed.
Abstract: A semiconductor device has an active region through which current flows and a termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer in the active region, a first parallel pn structure is provided including first columns of the first conductivity type and second columns of a second conductivity type disposed repeatedly alternating one another in a plane parallel to the front surface. In the termination structure region, a second parallel pn structure is provided including third columns of the first conductivity type and fourth columns of the second conductivity type disposed repeatedly alternating one another. On a surface of the second parallel pn structure, a first semiconductor region of the second conductivity type is provided including plural regions apart from one another.
Abstract: A first portion of the poly-silicon layer is provided on a first face of a front surface of a semiconductor substrate via a gate insulating film in an edge termination region and configures a gate runner. The first portion opposes an edge p++-type contact region in a depth direction Z. A chip-end-side edge of the first portion is positioned within a plane of the edge p++-type contact region. A field oxide film disposed separated from the poly-silicon layer, extends from a chip end toward a chip center and, on the first face, terminates closer to the chip end than does the first portion. The entire surface of the poly-silicon layer is flat, free of a step due to the field oxide film. A chip-center-side edge of the field oxide film is closer to the chip end than is the edge p++-type contact region and positioned on a p-type base region.
Abstract: A case of a semiconductor device has sidewall portions which surround sides of a metal substrate along the sides and a coating portion which covers the front surface of the metal substrate surrounded by the sidewall portions and which has through ring holes corresponding to fixing holes. Protrusions are formed on inner surfaces of the sidewall portions opposed to one another in plan view with the ring holes therebetween. The metal substrate is inserted in this way into an area surrounded by the sidewall portions of the case and is reliably fixed. Furthermore, alignment is performed with accuracy between each fixing hole of the metal substrate inserted in this way and its corresponding ring hole of the case.
Abstract: A rotor core (21) in a permanent magnet type rotating electric machine (1) is formed by laminating a plurality of plate materials (21A), (21B), (21C), and (21D) and includes one or a plurality of center bridges (26) formed between adjacent magnet slots (23) to couple an outer peripheral edge (24) and a core portion (25) together in one magnetic pole. Non-magnetic portions (30) are formed at a part or all of the one or the plurality of respective center bridges (26). Insulation films (32) are disposed on surfaces of parts other than regions where the non-magnetic portions (30) are formed on the plurality of respective plate materials (21A), (21B), (21C), and (21D) forming the rotor core (21).
Abstract: System and method for treating scrubber and ballast wastewater at the same time. The method includes mixing ballast and scrubber wastewater to make a suspended solid concentration or turbidity of the obtained wastewater mixture constant, the scrubber wastewater produced by bringing exhaust gas and scrubber washing water into contact with each other in a scrubber; adding magnetic powder to the wastewater mixture; and magnetically separating magnetic flocs obtained in the adding. The system includes a mixer that mixes ballast and scrubber wastewater to make a suspended solid concentration or turbidity of the obtained wastewater mixture constant, the scrubber wastewater produced by bringing exhaust gas and scrubber washing water into contact with each other in a scrubber; a magnetic powder adding device that adds magnetic powder to the wastewater mixture obtained by the mixer; and a magnetic separator that magnetically separates magnetic flocs obtained by the magnetic powder adding device.
June 28, 2018
Date of Patent:
October 13, 2020
FUJI ELECTRIC CO., LTD., UTSUNOMIYA UNIVERSITY
Abstract: A drive circuit of a power device, including an internal power supply, a set-side pulse generation circuit and a reset-side pulse generation circuit that are connected to the internal power supply, for generating a set signal and a reset signal respectively upon detecting that a logic input signal changes from a first logic level to a second logic level, or changes from the second logic level to the first logic level, a set-side level shift circuit and a reset-side level shift circuit that respectively level-shift the set signal and the reset signal, a control circuit that turns on and off the power device respectively responsive to the level-shifted set signal and the level-shifted reset signal, and an ensuring circuit that ensures a first state and a second state, in which the power device is respectively off and on, when the logic input signal is at the first logic level and the second logic level.
Abstract: A semiconductor device having an active region and a voltage withstand region comprises a first semiconductor layer of a first conductive type, a second semiconductor region of a second conductive type, disposed selectively on the front side of the first semiconductor layer, a plurality of first trench contact (TC) sections disposed at a peripheral section of the active region in the second semiconductor region, being apart from one another and extending in a first direction, a second trench contact (TC) disposed at the peripheral section of the active region in the second semiconductor region, extending in the first direction and being further from the voltage withstand region than the plurality of first trench contact sections, an electric conductor layer electrically connecting together the plurality of first TC sections, and a conductive connection region disposed between the first TC sections and second TC section, having a lower resistivity than the second semiconductor region, and electrically connecti
Abstract: A power module including a half bridge circuit having first and second switching elements respectively included in an upper arm and a lower arm thereof, and upper and lower arm drive circuits which respectively drive the first and second switching elements. The power module includes a first ground terminal on a ground side of the second switching element, a second ground terminal connected, via a first ground wiring, to the first ground terminal, a third ground terminal connected, via a second ground wiring including a dumping resistor, to the first ground terminal, a current detection circuit detecting a current flowing through the second switching element, and a control ground switching circuit which performs switching according to a value of the current detected by the current detection circuit, so as to connect a ground terminal of the lower arm drive circuit to the second or third ground terminal.
Abstract: A silicon carbide semiconductor substrate includes a silicon carbide substrate of a first conductivity type, an epitaxial layer of the first conductivity type provided on a front surface of the silicon carbide substrate, an impurity concentration of the epitaxial layer being 1×1017/cm3 to 1×1018/cm3, and a film thickness of the epitaxial layer being 1 ?m to 5 ?m. The silicon carbide semiconductor substrate further includes a buffer layer of the first conductivity type provided on a surface of a first side of the epitaxial layer opposite a second side facing the silicon carbide substrate, an impurity concentration of the buffer layer being about a same as that of the silicon carbide substrate, and a drift layer of the first conductivity type provided on a surface of a first side of the buffer layer opposite a second side facing toward the silicon carbide substrate, an impurity concentration of the drift layer being lower than that of the buffer layer.
Abstract: A semiconductor device that can detect temperature appropriately is provided. A semiconductor device provided with a semiconductor substrate in which one or more transistor portions and one or more diode portions are provided is provided, including: a temperature detecting portion provided above the top surface of the semiconductor substrate and having a longitudinal side in a predetermined longitudinal direction; a top surface electrode provided above the top surface of the semiconductor substrate; and one or more external lines that have a connecting part connected with the top surface electrode and electrically connect the top surface electrode to a circuit outside the semiconductor device. The temperature detecting portion extends across the one or more transistor portions and the one or more diode portions in the longitudinal direction, and the connecting part of at least one of the external lines is arranged around the temperature detecting portion when seen from above.
Abstract: An integrated circuit device includes a circuit device main body which is configured to execute a predetermined processing function, a communication control circuit which is configured to perform data communication with an external control device and an operation mode determination unit which is configured to selectively determine a normal mode for executing the processing function or a debug mode for setting an execution condition of the processing function as an operation mode of the circuit device main body. The operation mode determination circuit is configured to operate in accordance with an internal clock and to generate an operation mode output value for determining the operation mode of the circuit device main body according to a logical state of a particular one communication signal which is data-communicated with the external control device after a reset operation performed by a reset circuit is released.
Abstract: An uninterruptible power supply includes a power converter, a detector that detects a voltage value or a current value, and a controller that controls the power converter based on the detected voltage value or current value and generates one or more command values. The controller compares the one or more command values with predetermined reference values respectively corresponding to the one or more command values.
Abstract: An accumulation layer has a function of reducing an ON voltage (Von), which is a voltage between the collector and the emitter when turning on the IGBT, by accumulating carrier. However, when turning off the IGBT, the carrier contributes to a turn-off loss (Eoff). A semiconductor device is provided, comprising: a semiconductor substrate, wherein the semiconductor substrate includes: trench portions, a mesa portion each provided between two adjacent trench portions, and a drift layer, wherein the trench portions include: a gate trench portion, and a dummy trench portion, wherein the mesa portion has: an emitter region, a contact region, and a accumulation layer, wherein the number of accumulation layers provided in a depth direction in the mesa portion adjacent to the gate trench portion is larger than that of the accumulation layers provided in the depth direction in the mesa portion between the two dummy trench portions.
Abstract: A silicon carbide epitaxial substrate including a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, and a high-density foreign element region. The first semiconductor layer is provided at a front surface of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The high-density foreign element region is provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof. The high-density foreign element region contains an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.