Patents Assigned to Fuji Electric Co., Ltd.
  • Publication number: 20240120249
    Abstract: [Problem] An object of the present invention is to provide a semiconductor module capable of preventing a wire wiring from being broken because of a crack having occurred in sealing resin. [Solution] A semiconductor module 1 includes semiconductor chips 14a to 14d, sealing resin 18 configured to seal the semiconductor chips 14a to 14d, a case 11 including a casting area 117u, first portions 111 and 112, and second portions 113 and 114, wire wirings 101a to 101j and 102a to 102i sealed in the sealing resin 18 while being located closer to the first portion 111 and connected to the semiconductor chips 14a to 14d, and recessed portions 131a, 131b, 132a, and 132b formed on the second portions 113 and 114 between a virtual surface VSu and the first portion 112.
    Type: Application
    Filed: August 29, 2023
    Publication date: April 11, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato NAKANO
  • Patent number: 11955791
    Abstract: A short-circuit detector includes: a first Rogowski coil configured to generate a first detection signal in accordance with a current that flows through a first arm due to a short circuit in a load; a second Rogowski coil configured to generate a second detection signal in accordance with a current that flows through the first arm due to a short circuit in the first arm or a second arm; a load short-circuit detection circuit configured to detect the short circuit in the load, based on the first detection signal; an arm short-circuit detection circuit configured to detect the short circuit in the first arm or the second arm, based on the second detection signal; and a short-circuit detection circuit configured to detect a short-circuit, based on: an output signal output from the load short-circuit detection circuit; and an output signal output from the arm short-circuit detection circuit.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Natsuko Takeuchi, Kunio Matsubara, Hiromu Takubo
  • Patent number: 11955540
    Abstract: Provided is a semiconductor device, comprising a semiconductor substrate; and an emitter electrode provided above an upper surface of the semiconductor substrate; wherein the semiconductor substrate has: a first conductive type drift region; a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate; a second conductive type contact region with a higher doping concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate; a trench contact of a conductive material provided to connect to the emitter electrode and penetrate the contact region; and a second conductive type high-concentration plug region with a higher doping concentration than the contact region, which is provided in contact with a bottom portion of the trench contact.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Patent number: 11955398
    Abstract: A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Eri Ogawa
  • Publication number: 20240113628
    Abstract: An integrated circuit for a power supply circuit that generates an output voltage, and that includes: a transformer including primary and secondary coils, first and second transistors controlling a current of the primary coil, and a resonant circuit including the primary coil and a first capacitor. The integrated circuit controls the first and second transistors. The integrated circuit includes: a voltage generator circuit supplying a first current to a second capacitor, and to generate a first voltage at the second capacitor; a driving signal output circuit outputting a driving signal for driving the first and second transistors, based on the first voltage and a feedback voltage corresponding to the output voltage; and a control circuit controlling the voltage generator circuit such that, when the output voltage drops and a derivative of the feedback voltage at a time point is greater than a predetermined value, the first current increases and then decreases.
    Type: Application
    Filed: August 22, 2023
    Publication date: April 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshizawa TSUYOSHI
  • Publication number: 20240109157
    Abstract: In an example, use of a solder joint may include a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface of the joined body in contact with the solder joint layer. The Ni—P—Cu plating layer may contain Ni as a main component and may contain 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, and the Ni—P—Cu plating layer may have a microcrystalline layer at an interface with the solder joint layer.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko WATANABE, Shunsuke SAITO, Takeshi YOKOYAMA
  • Publication number: 20240112991
    Abstract: A semiconductor module includes: a stacked substrate; a semiconductor element arranged on an upper surface of the first circuit board; a metal wiring board including a first bonding portion bonded to an upper surface of the semiconductor element with a bonding material; and a sealing resin that seals the stacked substrate, the semiconductor element, and the metal wiring board. The first bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The metal wiring board has a first standing portion standing up from one end of the first bonding portion, and a second standing portion standing up from the other end of the first bonding portion. The first standing portion constitutes a part of a wiring path through which a main current flows. The second standing portion constitutes a non-wiring path through which the main current does not flow.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Mai SAITO, Yoko NAKAMURA
  • Patent number: 11949347
    Abstract: A power conversion device includes a power converter to output AC power by converting input DC power, an electric leakage detector to detect electric leakage in a power supply line through which the AC power output by the power converter flows when the AC power is being output by the power converter, and a power conversion controller configured to control power conversion of the power converter. The power conversion controller is configured to stop power conversion operation of the power converter based on a detection result of the electric leakage detector.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignees: FUJI ELECTRIC CO., LTD., HONDA MOTOR CO., LTD.
    Inventors: Nobuhisa Ando, Hiroki Katsumata, Masahiko Sato
  • Patent number: 11949005
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Takahashi, Yuichi Harada, Kouta Yokoyama
  • Patent number: 11949338
    Abstract: A power converter includes a positive busbar electrically connected to a positive terminal and the first capacitor electrode, and includes a negative busbar electrically connected to a negative terminal and the second capacitor electrode. The power converter includes output busbars each electrically connected to a given output terminal among multiple output terminals, a given high-side switching element among a plurality of high-side switching elements, and a given low-side switching element among a plurality of low-side switching elements. The power converter includes a cooler that cools the high-side switching elements and the low-side switching elements. The power converter includes a housing that accommodates a supply tube and a discharge tube. The positive terminal, the negative terminal, the output terminals, the inlet port, and the outlet port are exposed on the housing. The inlet port, the outlet port, the supply tube, and the discharge tube are separate members from the housing.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuji Suzuki, Motohito Hori, Akio Toba, Ikuya Sato, Yasuhito Tanaka, Masamichi Iwasaki, Masaaki Ajima, Nobuaki Ohguri
  • Patent number: 11948937
    Abstract: A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity-type; a bottom surface electrode to which a first potential is applied, the bottom surface electrode being provided on a bottom surface of the semiconductor base body; a first well of a second conductivity-type to which a second potential lower than the first potential is applied, the first well being provided on a top surface side of the semiconductor base body; a second well of the first conductivity-type provided in the first well; and an edge structure provided in the first well and configured to supply a third potential higher than the second potential to the second well.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki Toyoda
  • Patent number: 11948976
    Abstract: A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Koichi Murata
  • Publication number: 20240106334
    Abstract: A switching control circuit for a power supply circuit that includes a transformer including primary and secondary coils, and first and second transistors controlling a current flowing through the primary coil. The power supply circuit generates an output voltage at a target level. The switching control circuit controls switching of the first and second transistors. The switching control circuit includes: a drive signal output circuit configured to output drive signals according to a normal mode, when the output voltage is lower than a first level, and output the drive signals according to a burst mode, when the output voltage is higher than the first level; and a driver circuit configured to switch the first and second transistors in response to the drive signals. The drive signal output circuit reduces a first time period in the burst mode, in response to the output voltage rising above the first level.
    Type: Application
    Filed: August 24, 2023
    Publication date: March 28, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroaki MATSUMOTO, Jun ASAI
  • Publication number: 20240105858
    Abstract: A silicon carbide semiconductor device includes an active region, a first-conductivity-type region, and a termination region. The active region has first second-conductivity-type regions and first silicide films in trenches, second second-conductivity-type regions and a second silicide film between the trenches that are adjacent to one another, and a first electrode while the termination region has a third second-conductivity-type region. The active region includes ohmic regions, non-operating regions and Schottky regions, each of which has a stripe shape. Each ohmic region is a region where the first electrode is in contact with either the first silicide film or the second silicide film. Each non-operating region is a region where the first electrode is in contact with either the first or second second-conductivity-type regions. Each Schottky region is a region where the first electrode forms a Schottky barrier junction with the first-conductivity-type region.
    Type: Application
    Filed: July 25, 2023
    Publication date: March 28, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi HASHIZUME
  • Patent number: 11942535
    Abstract: Provided is a semiconductor device that includes a drift region that is of a first conductivity type and is provided in a semiconductor substrate; a base region that is of a second conductivity type and is provided above the drift region; an accumulation region that is of the first conductivity type provided between the base region and the drift region; and an electric field relaxation region that is provided between the base region and the accumulation region, wherein the boundary between the electric field relaxation region and the accumulation region is a location for a half-value for the peak of the doping concentration of the accumulation region, and an integrated concentration of the electric field relaxation region is greater than or equal to 5E14 cm?2 and less than or equal to 5E15 cm?2.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: March 26, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yosuke Sakurai, Yuichi Onozawa
  • Publication number: 20240094649
    Abstract: An electrophotographic photoconductor including a sequentially-provided conductive substrate, an undercoat layer, and a photosensitive layer. Photosensitive layer is a negatively-charged stacked type including a charge generation layer and a charge transport layer. Undercoat layer contains a resin binder and a first filler, the first filler including a zinc oxide particle surface-treated with an N-acylated amino acid or an N-acylated amino acid salt, and the charge generation layer containing an adduct compound of titanyl phthalocyanine and butanediol.
    Type: Application
    Filed: February 28, 2023
    Publication date: March 21, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Fengqiang ZHU, Shinjiro SUZUKI, Masaru TAKEUCHI
  • Publication number: 20240096764
    Abstract: A semiconductor device includes an insulated circuit board having a semiconductor chip thereon, a W-phase output terminal electrically connected to the chip, a cooling device including a cooling top plate having a top surface on which the insulated circuit board is disposed, and a case including a frame portion on the cooling top plate and having an open storage area in which the insulated circuit board is stored, and a current detection unit for detecting an output current flowing through the output terminal. The output terminal extends from the unit storage portion to an outside the case and passes through the current detection unit. The current detection unit is embedded within the frame portion such that a shortest external dimension thereof is parallel to a first direction that is perpendicular to the top surface in the cooling area of the cooling top plate.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 21, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichiro ADACHI
  • Publication number: 20240097015
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity-type: an insulated gate electrode structure buried in a first trench provided in the semiconductor substrate; a base region of a second conductivity-type provided in the semiconductor substrate so as to be in contact with the first trench; a first main electrode region of the first conductivity-type provided at an upper part of the base region so as to be in contact with the first trench: a polysilicon film of the second conductivity-type having a higher impurity concentration than the base region and buried in a second trench provided in the semiconductor substrate so as to be in contact with the base region; and a second main electrode region provided on a bottom surface side of the semiconductor substrate.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 21, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryouichi KAWANO, Motoyoshi KUBOUCHI
  • Publication number: 20240096990
    Abstract: On a surface of a portion of a front electrode exposed in an opening of a passivation film, a Ni-deposited film having high solder wettability is provided apart from the sidewalls of the opening of the passivation film. Metal wiring is soldered to the Ni-deposited film. The solder layer is formed only on the Ni-deposited film and thus, the solder layer and the passivation film do not contact each other. The front electrode contains Al and an entire area of the surface of the front electrode excluding the portion where the Ni-deposited film is formed is covered by a surface oxide film that is constituted by an aluminum oxide film formed by intentionally oxidizing the surface of the front electrode. The surface oxide film intervenes between the front electrode, the passivation film, and a sealant, whereby the adhesive strength of the passivation film and the sealant is increased.
    Type: Application
    Filed: July 26, 2023
    Publication date: March 21, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Tomohiro MORIYA
  • Publication number: 20240097556
    Abstract: An object of the present disclosure is to provide a semiconductor module capable of reducing variation in drive characteristics of each of plural semiconductor switching elements. A semiconductor module includes IGBTs configured to supply power to a load and gate driver circuits in which drive targets are set in a one-to-one relationship to the IGBTs and in which according to a positional relationship to, for example, the IGBT as the drive target, a driving capability of the gate driver circuit to drive the IGBT is set.
    Type: Application
    Filed: August 23, 2023
    Publication date: March 21, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Isao KAKEBE