Patents Assigned to Fuji Electric Co., Ltd.
  • Publication number: 20210376738
    Abstract: A switching control circuit for controlling an LLC converter that includes a first switching device, a first free-wheeling diode connected in parallel with the first switching device, a second switching device connected in series with the first switching device and the first free-wheeling diode, and a second free-wheeling diode connected in parallel with the second switching device. The switching control circuit is configured to control switching of the first and second switching devices.
    Type: Application
    Filed: March 25, 2021
    Publication date: December 2, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryuunosuke ARAUMI, Ryuji YAMADA
  • Publication number: 20210375855
    Abstract: A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.
    Type: Application
    Filed: March 31, 2021
    Publication date: December 2, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi NISHIMURA
  • Publication number: 20210376132
    Abstract: A semiconductor device includes a plurality of first trenches each having a stripe-shape, extending in parallel to each other, a first mesa region, a second mesa region, a first interlayer insulating film covering the first mesa region and the second mesa region, and a first contact hole penetrating the first interlayer insulating film to the first mesa region, and extending along a longitudinal direction of the first trenches. The first mesa region includes emitter regions of a first conductivity type periodically provided along the longitudinal direction of the first trenches in a plan view, contact regions of a second conductivity type provided such that each of the emitter regions is interposed between the contact regions along the longitudinal direction in the plan view, and a base region of the second conductivity type provided immediately below the emitter regions and the contact regions.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hitoshi ABE, Hiroshi MIYATA, Hidenori TAKAHASHI, Seiji NOGUCHI, Naoya SHIMADA
  • Publication number: 20210375832
    Abstract: A semiconductor device including a semiconductor chip, an insulating circuit board having a circuit pattern formed on an insulating plate, a case including a frame part having an opening that is substantially rectangular in a plan view of the semiconductor device, inner wall surfaces of the frame part at the opening forming a storage part to store the insulating circuit board, and a printed circuit board which has a flat plate shape and which protrudes from one of the inner wall surfaces of the frame part toward the storage part. The semiconductor device further includes a sealing material filled in the storage part, to thereby seal the semiconductor chip and the printed circuit board. A front surface of the sealing material forms a sealing surface, and in a thickness direction of the semiconductor chip, the sealing surface is higher around the printed circuit board than around the semiconductor chip.
    Type: Application
    Filed: March 26, 2021
    Publication date: December 2, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato NAKANO
  • Publication number: 20210375734
    Abstract: A semiconductor device, including a circuit pattern, a contact part and an external connection terminal. The contact part has a cylindrical through-hole and first and second opening ends opposite to each other, the second opening end being joined to the circuit pattern. The external connection terminal has a prismatic main body portion and first and second end portions, the second end portion being inserted into the through-hole from the first opening end of the contact part. The main body portion of the external connection terminal has an insertion prevented portion formed thereon. The contact part includes an insertion preventing portion formed on an inner circumferential surface of the through-hole, the insertion preventing portion being so positioned as to be substantially downstream, with respect to an insertion direction of the external connection terminal, from the main body portion of the external connection terminal inserted into the through-hole.
    Type: Application
    Filed: March 26, 2021
    Publication date: December 2, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Seiichi TAKAHASHI
  • Publication number: 20210375786
    Abstract: A semiconductor module includes semiconductor elements, a case that houses the semiconductor elements, an external terminal electrically connecting the semiconductor elements and an external conductor, and a nut into which a bolt that secures the external conductor and the external terminal is threaded. The nut includes a cylindrical main body having a threaded hole, and a flange projecting in a direction radially outward of a center axis of the threaded nut hole and being disposed on one face of the main body. The case includes a wall surrounding the nut, the wall having a first recess that houses the main body, a second recess above the first recess and housing the flange, and a notch cut in a portion of the wall surrounding the main body. The first recess extends deeper than the main body, and the fillet is formed on a floor surface of the first recess.
    Type: Application
    Filed: March 30, 2021
    Publication date: December 2, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Satoshi KANEKO, Hisato INOKUCHI
  • Patent number: 11189547
    Abstract: A semiconductor module includes a laminated substrate that includes a heat radiating plate, and an insulation layer having a conductive pattern thereof and being disposed on a top surface of the heat radiating plate, a semiconductor element disposed on a top surface of the conductive pattern, an integrated circuit that controls driving of the semiconductor element, a control-side lead frame having a primary surface on which the integrated circuit is disposed, and a mold resin that seals the laminated substrate, the semiconductor element, the integrated circuit, and the control-side lead frame. The control-side lead frame has a rod-shaped first pin having a first end, a first end side of the first pin extending toward the top surface of the heat radiating plate, and the heat radiating plate has at least one insertion hole into one of which the first end of the first pin is press-fitted.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Nobuhiro Higashi
  • Patent number: 11189685
    Abstract: Provided is a resistance element, including: a semiconductor substrate; a first insulating film stacked on the semiconductor substrate; a resistance layer selectively stacked on the first insulating film; a first auxiliary film separated from the resistance layer; a second auxiliary film separated from the resistance layer in a direction different from that of the first auxiliary film; a second insulating film stacked on the first insulating film to cover the resistance layer, and the first auxiliary film and the second auxiliary film; a first electrode connected to the resistance layer and stacked on the second insulating film disposed on an upper side of the first auxiliary film; and a second electrode connected to the resistance layer by being separated from the first electrode and stacked on the second insulating film on the upper side of the second auxiliary film.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaru Saito, Masaharu Yamaji, Osamu Sasaki, Hitoshi Sumida
  • Patent number: 11188137
    Abstract: A slave communication apparatus including a clock recovering section that recovers a clock signal from a transmission signal having a first signal value when the clock is a first level, a second signal value when the clock is a second level and data has a first data value, and a third signal value between the first and second signal values when the clock is the second level and the data has a second data value; and a data recovering section that recovers the data, wherein the data recovering section sets the data threshold value to be a first setting value between the second and third signal values in response to the recovered data having the second data value, and sets the data threshold value to be a second setting value between the first and third signal values in response to the recovered data having the first data value.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 11185186
    Abstract: A beverage extraction device includes a mesh member, a cover member that is movable between a first position and a second position; a scraper portion, an upper end portion of which is pivotally supported by the cover member with a lower end portion of the scraper portion being swingable along a vertical direction, that takes a basic attitude in which the lower end portion is positioned lower than the upper end portion under a normal condition, the lower end portion being configured to slide on the mesh member when the cover member is moved from the first position toward the second position; and a contact member configured to come into contact with the scraper portion sliding on the mesh member to cause the scraper portion to take an attitude in which the lower end portion swings upward when the cover member approaches the second position.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yohei Nishikawa
  • Patent number: 11189534
    Abstract: A semiconductor assembly is provided, that includes a semiconductor chip including an upper surface electrode and a lower surface electrode opposite to the upper surface electrode, a metallic wiring plate electrically connected to the semiconductor chip, and a soldering portion that bonds the upper surface electrode of the semiconductor chip to the metallic wiring plate by soldering, the semiconductor chip including a temperature detection portion, an anode wire for the temperature detection portion, and a first insulation layer that blocks the soldering portion and insulates the soldering portion from the anode wire.
    Type: Grant
    Filed: January 26, 2020
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiichi Higuchi
  • Patent number: 11189579
    Abstract: A semiconductor module internally includes semiconductor elements and multilayer substrates on which the semiconductor elements are arranged. The semiconductor module further includes, in a case, fastening portions for fastening a cooler such as conductive radiating fins or water-cooling jackets, for example. In the semiconductor module, side faces of heat radiating plates formed on the rear surface sides of the multilayer substrates are electrically connected to the fastening portions in the case by conductive connectors.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Satoshi Kaneko, Naoyuki Kanai
  • Patent number: 11189723
    Abstract: A semiconductor device including a semiconductor substrate, a first semiconductor layer provided on a main surface of the semiconductor substrate, a second semiconductor layer selectively provided on a surface of the first semiconductor layer, a plurality of first and second semiconductor regions selectively provided in the second semiconductor layer at a surface thereof, and a plurality of trenches provided in a striped pattern that extends in a first direction.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Hoshi
  • Patent number: 11189608
    Abstract: A semiconductor device includes circuit substrates 3 and 9 including circuit pattern layers 3c/9b, a semiconductor element 5 mounted to the circuit pattern layer 3c, a connecting pin 7 connecting the semiconductor element 5 to the circuit pattern layer 9b, a pin-shaped terminal 17 connected to the circuit pattern layer 9b, a sealing member 2 sealing the circuit substrates 3 and 9, the semiconductor element 5, and the connecting pin 7, and an external terminal 27 including a flat plate portion 27s and an extending portion 27t bent from the flat plate portion 27s and extends away from the circuit substrate 9, in which the flat plate portion 27s is connected to the pin-shaped terminal 17 and arranged in parallel with the circuit pattern layer 9b, and the extending portion 27t is provided in a range of a width in a transverse direction of the sealing member 2.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hideyo Nakamura, Motohito Hori, Yuki Inaba
  • Patent number: 11191157
    Abstract: A semiconductor device, including a first board, a second board having a plurality of through holes passing therethrough, and a plurality of external terminals that are respectively press-fitted into the plurality of through holes of the second board, one end portion of each external terminal passing through the corresponding through hole and being fixed to a front surface of the first board. The second board is a printed circuit board that further includes, in a top view thereof, a plurality of support regions, each having one of the plurality of through holes formed therein, and a plurality of buffer regions respectively surrounding the plurality of support regions, each buffer region having at least one buffer hole and at least one torsion portion formed therein, the at least one torsion portion being connected to the support region surrounded by each buffer region.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toshiyuki Miyasaka, Yuichiro Hinata
  • Publication number: 20210366796
    Abstract: A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.
    Type: Application
    Filed: April 1, 2021
    Publication date: November 25, 2021
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Nobuhiro HIGASHI
  • Patent number: 11183601
    Abstract: A semiconductor device includes a semiconductor substrate including a drift region of a first conductivity type, a transistor portion provided in the substrate, and an adjacent element portion provided in the substrate, the adjacent element and transistor portions being arranged along an arrangement direction. The transistor and adjacent element portions both include a base region of a second conductivity type provided above the drift region, trench portions formed through the base region, extending in an extending direction orthogonal to the arrangement direction on the upper surface, and having a conducting portion therein, and a first lower surface side lifetime control region provided, on a lower surface side, continuously from the transistor portion to the adjacent element portion and includes a lifetime killer. The lifetime control region is provided over entirety of the transistor portion and in a part of the adjacent element portion in a top view of the substrate.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11183476
    Abstract: A silicon carbide semiconductor device including a semiconductor substrate containing silicon carbide, a contact electrode, which is a silicide layer containing nickel, provided on a surface of the semiconductor substrate and forming an ohmic contact with the semiconductor substrate, and a metal connection layer provided on a surface of the contact electrode. The metal connection layer has a stacked structure in which on the surface of the contact electrode, a titanium layer, a nickel layer, and a gold layer are sequentially stacked. The titanium layer includes a carbon diffusion layer formed along an interface between the titanium layer and the contact electrode, a concentration of carbon being higher in the carbon diffusion layer than in a portion of the titanium layer other than the carbon diffusion layer. The titanium layer, the nickel layer and the gold layer have thicknesses of 100 nm to 300 nm, 1000 nm to 1500 nm, and 20 nm to 200 nm, respectively.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yoshiyuki Sakai
  • Patent number: 11183494
    Abstract: A semiconductor integrated circuit including a power switch element, a control circuit connected to the power switch element, an electrostatic discharge protection device connected to an input terminal to which an input voltage is applied, for protecting the power switch element and the control circuit from being damaged by an electrostatic discharge, and a short-to-supply fault protection circuit connected to the electrostatic discharge protection device, for protecting the power switch element and the control circuit from being damaged by a high voltage. The short-to-supply fault protection circuit includes a first step-down circuit disposed between the input terminal and the control circuit, and a second step-down circuit disposed between the input terminal and a gate of the power switch element. Each of the first and second step-down circuits, upon detecting the high voltage, steps down the high voltage for the control circuit or the power switch element.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: November 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takanori Kohama
  • Patent number: 11183388
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: November 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa, Misaki Takahashi