Patents Assigned to Fuji Electric Co., Ltd.
  • Publication number: 20190181008
    Abstract: Laser light of a short-wavelength laser is irradiated from a rear surface of an n?-type semiconductor substrate, activating a p+-type collector region and an n+-type cathode region. At this time, a surface layer at the rear surface of the n?-type semiconductor substrate is melted and recrystallized, eliminating amorphous parts. Thereafter, laser light of a long-wavelength laser is irradiated from the rear surface of the n?-type semiconductor substrate and an n-type FS region is activated. Substantially no amorphous parts exist in the surface layer at the rear surface of the n?-type semiconductor substrate. Therefore, decreases in the absorption rate and increases in the reflection rate of the laser light of the long-wavelength laser are suppressed and heat from the laser light of the long-wavelength laser is transmitted to the n-type FS region, enabling the n-type FS region to be assuredly activated by laser annealing using lower energy.
    Type: Application
    Filed: February 19, 2019
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi TAKISHITA, Takashi YOSHIMURA
  • Publication number: 20190181089
    Abstract: A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.
    Type: Application
    Filed: October 26, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Taichi Karino, Hitoshi Sumida, Masaru Saito, Masaharu Yamaji, Osamu Sasaki
  • Publication number: 20190181252
    Abstract: An IGBT includes current sense cell having a sensing area for sensing a current flowing an active area and an extraction area for extracting a hole current. The extraction area around the sensing area, has a portion in a gate trench is not in contact with the emitter region, and a p-type well region provided deeper than the first trench and having a high impurity concentration. An area of the extraction area is four times or more and 10,000 times or less an area of the sensing area.
    Type: Application
    Filed: October 26, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Tohru SHIRAKAWA
  • Publication number: 20190181216
    Abstract: A resistive element includes: a resistive layer having a rectangular shape defined by a resistance length direction and a resistance width direction orthogonal to the resistance length direction; a first outer contact and a first inner contact allocated on one side of the resistive layer defined in the resistive length direction; and a second outer contact and a second inner contact allocated on another side of the resistive layer defined in the resistive length direction, wherein, as viewed in the resistance length direction, the first inner contact is shifted from the second inner contact, the first inner contact is at least partly opposed to the second outer contact, and the second inner contact is at least partly opposed to the first outer contact.
    Type: Application
    Filed: October 24, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaru SAITO
  • Publication number: 20190181260
    Abstract: A semiconductor device has an active region through which current flows and a termination structure region. At a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. At a surface of the first semiconductor layer, a lower parallel pn structure is provided. At a surface of the lower parallel pn structure, an upper parallel pn structure is provided in the termination structure region and a first semiconductor region of a second conductivity type is provided in the active region. A width of an upper second column is wider than a width of a lower second column. An interval between the upper second columns is wider than an interval between the lower second columns. A thickness of the upper second column is thicker than a thickness of the first semiconductor region.
    Type: Application
    Filed: October 24, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Ryo Maeta
  • Publication number: 20190181261
    Abstract: An insulated-gate semiconductor device includes: an n-type current spreading layer provided on an n?-type drift layer; a p+-type base region provided on the current spreading layer; an n+-type source region provided in an upper portion of the base region; an insulated-gate electrode structure provided inside a trench; a p+-type gate-bottom protection-region provided in the current spreading layer so as to be in contact with a bottom of the trench; and a p+-type base-bottom buried-region buried in the current spreading layer, having a bottom surface having the same depth as a bottom surface of the gate-bottom protection-region, wherein the base-bottom buried-region is divided into a plurality of portions in a depth direction through an n-type separation layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20190181229
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Application
    Filed: October 25, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 10319665
    Abstract: A cooler for cooling a semiconductor module to be secured to a base, the cooler including: a cooler body that includes a refrigerant flow path surrounded by a first wall part having a first through-hole, a second wall part that is arranged facing the first wall part and that includes a connection region which is to be connected to the base at a position opposing the first through-hole, and a side wall part for connecting the periphery of the first wall part and the periphery of the second wall part; and a lid for closing off the first through-hole.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Ryo Maruyama
  • Patent number: 10319808
    Abstract: A semiconductor device is provided, including a semiconductor substrate; a first conductivity type drift region provided inside the semiconductor substrate; a plurality of gate trench portions provided extending from an upper surface of the semiconductor substrate and reaching the drift region; a dummy trench portion provided between two gate trench portions and provided extending from the upper surface of the semiconductor substrate and reaching the drift region; a second conductivity type base region provided: in a region of the semiconductor substrate adjacent to any of the gate trench portions; and between the upper surface of the semiconductor substrate and the drift region; and a second conductivity type first well region provided: in a region of the semiconductor substrate adjacent to the dummy trench portion; and reaching a position deeper than a lower end of the dummy trench portion; and having a doping concentration higher than that of the base region.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10319820
    Abstract: A semiconductor device includes a silicon carbide semiconductor substrate, a first silicon carbide layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The third semiconductor region is thicker than the second semiconductor region and a width of a side of the third semiconductor region facing the first semiconductor region is narrower than a width of a side thereof facing the source electrode.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Yasuyuki Hoshi, Yasuhiko Oonishi, Yuichi Harada
  • Patent number: 10320278
    Abstract: There is provided a semiconductor device capable of decreasing a switching loss. The semiconductor device has first semiconductor elements (Su)-(Sw) and second semiconductor elements (Sx)-(Sz) connected in series, in which the first semiconductor element includes a low switching loss semiconductor element having a switching loss which is smaller than a switching loss of the second semiconductor element and the second semiconductor element includes a low conduction loss semiconductor element having a conduction loss which is smaller than a conduction loss of the first semiconductor element.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Ryu Araki
  • Patent number: 10319824
    Abstract: A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n?-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Akimasa Kinoshita, Yasuhiko Oonishi
  • Publication number: 20190172912
    Abstract: A method of evaluating an insulated-gate semiconductor device having an insulated-gate structure including a channel formation layer made of a wide-bandgap semiconductor and a gate insulating film formed contacting the channel formation layer includes removing the gate insulating film in order to expose a surface of the channel formation layer; taking a phase image of the exposed surface of the channel formation layer using a phase mode of an atomic force microscope; evaluating a surface condition of the exposed surface of the channel formation layer by calculating an evaluation metric from phase shift values in the phase image and by determining whether the evaluation metric satisfies a prescribed condition; and determining that the insulated-gate semiconductor device is acceptable when the evaluation metric satisfied the prescribed condition.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 6, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Takayuki HIROSE, Yutaka TERAO, Aki TAKIGAWA, Etsuko TOMITA
  • Publication number: 20190173463
    Abstract: A driving circuit that drives an insulated-gate semiconductor device. The driving circuit includes a constant-current generation circuit and a discharge circuit. The constant-current generation circuit has first and second transistors forming a current mirror, and a constant-current circuit connected to the drain of the first transistor for providing a constant current to the current mirror. The discharge circuit is connected to a gate of the insulated-gate semiconductor device and the drain of the second transistor, and includes a third transistor. The discharge circuit is configured to draw out a current injected into the gate of the insulated-gate semiconductor device by inputting a driving signal to the gate of the third transistor, and correct a metal-oxide-semiconductor (MOS) size of the third transistor so as to adjust an amount of a current that flows via the drain and the source of the third transistor to ground.
    Type: Application
    Filed: January 28, 2019
    Publication date: June 6, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takahiro MORI
  • Publication number: 20190173660
    Abstract: A system is connected to a single-wire communication line to perform bidirectional communication between a master side and a slave side, and an input clock-side transistor connected between a GND level and the communication line performs switching according to an input clock. A first transistor is connected between a first potential and the communication line, a second transistor has one end connected to a second potential, and a master-side resistor is connected between the other end of the second transistor and the other end of a third transistor. A fourth transistor is connected between the communication line and a third potential equal to or higher than the first potential, and a slave-side resistor is connected between the communication line and the GND level.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 6, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi AKAHANE
  • Publication number: 20190172944
    Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.
    Type: Application
    Filed: November 6, 2018
    Publication date: June 6, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Publication number: 20190172900
    Abstract: Warping of a semiconductor wafer occurring due to a difference in the thermal expansion rates of an insulating film and the semiconductor wafer is restricted. Therefore, processing failures and conveying failures in the manufacturing process, as well as cracking of the semiconductor wafer, are restricted. Provided is a high breakdown voltage passive element including a substrate, a lower metal layer and upper metal layer stacked on the substrate, and an insulating unit formed between the lower metal layer and upper metal layer, wherein the insulating unit has a first insulating film whose thermal expansion rate is lower than the thermal expansion rate of the substrate, and a second insulating film, formed on the first insulating film, whose thermal expansion rate is higher than the thermal expansion rate of the substrate.
    Type: Application
    Filed: February 5, 2019
    Publication date: June 6, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Masaharu Yamaji
  • Patent number: 10312343
    Abstract: A device includes a vertical semiconductor switch including (i) a gate terminal and a first terminal provided on a substrate and (ii) a second terminal provided on the substrate, where the vertical semiconductor switch is configured to electrically connect or disconnect the first terminal and the second terminal, a first insulative film provided on the substrate, a second insulative film provided on the substrate, where the second insulative film is in contact with the first insulative film and thinner than the first insulative film, and a zener diode formed on the first insulative film and the second insulative film, where the zener diode includes a first portion that is formed on the first insulative film and connected to the first surface of the substrate and a second portion that is formed on the second insulative film and connected to the gate terminal.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 4, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shigemi Miyazawa
  • Patent number: 10312800
    Abstract: An AC-DC converter that converts a rectified voltage of an AC power supply AC to a DC output voltage by switching ON and OFF a switching device and controls the switching device by using a command value for and a detected value of the DC output voltage as well as a detected value of a reactor current includes: a current sense resistor and a low-pass filter for detecting a rectified current; a proportional controller that multiplies the detected value of the rectified current by a prescribed gain; an output voltage command calculator such as a divider that calculates an output voltage command for the switching device on the basis of an output of the proportional controller; and a circuit that compares the output voltage command to a carrier signal in order to generate a gate signal for the switching device, wherein the prescribed gain is effectively adjusted on the basis of a difference signal between a command value for and a detected value of the DC output voltage.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 4, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Ryuji Yamada
  • Patent number: 10312727
    Abstract: In power supply devices, it is prevented to cool the components that actually do not need to be cooled. A power supply device includes a first converter configured to convert AC power from an AC power source into DC power, a second converter configured to convert a voltage to charge a backup electrical storage unit with the DC power from the first converter and to cause the electrical storage unit to discharge DC power, a plurality of cooling units configured to individually cool the first converter and the second converter, and a controller configured to change an operational state of the plurality of cooling units depending on an operational status of the power supply device.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: June 4, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroyuki Kobayashi, Hiromu Takubo