Abstract: A semiconductor device, including: a semiconductor chip including a switching element, the switching chip having a first control electrode formed on a front surface thereof; and a mirror clamping circuit including a mirror clamping circuit switching element that is located on the first control electrode of the semiconductor chip. The semiconductor chip and the mirror clamping circuit switching element are incorporated in a same package. The switching element is configured to operate in an on state and an off state. The mirror clamping circuit is configured to suppress a rise in a potential of the first control electrode of the switching chip when the switching element is in the off state.

Abstract: The semiconductor substrate has an active region, a termination regions surrounding a periphery of the active region, and a transition region between the active region and the termination region. The transition region has a portion that overlaps an outer peripheral portion of the active region by a predetermined width. The portion of the transition region includes at least one pair of one of the n-type column regions in the active region and an adjacent one of the p-type column regions in the active region. The parallel pn layer exhibits doping concentration distributions of n-type and p-type in each of which the doping concentration is relatively high in a center portion of the active region, progressively decreases in the transition region in a direction from the active region to the edge termination region, and is relatively high in the termination region.

Abstract: On a single semiconductor substrate, a main semiconductor device is provided in an active-region operating region and a current sensing portion for detecting overcurrent flowing through the main semiconductor device is provided in a sensing region. The main semiconductor device and the current sensing portion are vertical IGBTs with a trench gate structure. All cells of the main semiconductor device have a CS region. Some of the cells of the current sensing portion have the same structure as the structure of the cells of the main semiconductor device while some of the cells have a structure that is free of CS regions but otherwise the same as the structure of the cells of the main semiconductor device. An average carrier concentration of the CS regions per unit area of the sensing region is less than that of the CS regions per unit area of the active-region operating region.

Abstract: In an example, use of a solder joint may include a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface of the joined body in contact with the solder joint layer. The Ni—P—Cu plating layer may contain Ni as a main component and may contain 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, and the Ni—P—Cu plating layer may have a microcrystalline layer at an interface with the solder joint layer.

Abstract: A silicon carbide semiconductor device, including: a semiconductor substrate; a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, and a plurality of fourth semiconductor regions formed in the semiconductor substrate; a plurality of gate trenches penetrating through the second to fourth semiconductor regions, to reach the first semiconductor region; a plurality of first high concentration regions facing bottoms of the plurality of gate trenches. Each second semiconductor region is formed between adjacent two of the gate trenches. The silicon carbide semiconductor device has a double-gate structure in which a channel is formed over an entire area of each second semiconductor region, and is sandwiched by adjacent two of the gate trenches. Each first high concentration region has a width that is no more than a width of each gate trench, but is more than a distance between adjacent two of the gate trenches.

Abstract: A semiconductor device includes an output element, a temperature detection circuit, a current limiting circuit, and an overcurrent detection circuit. The output element is a power semiconductor element that drives a load, and is turned on by applying a predetermined turn-on voltage to a gate of the output element in a normal state. The temperature detection circuit detects the temperature of the output element as a detected temperature, during the operation of the output element. The overcurrent detection circuit detects an overcurrent state of the output element. When the overcurrent state is detected and the detected temperature exceeds a set temperature, the current limiting circuit sets a gate voltage of the output element to a set voltage lower than the predetermined turn-on voltage. In addition, the current limiting circuit increases the set voltage in stages as the temperature decreases.

Abstract: A semiconductor device includes, in an active region and a termination region of a semiconductor substrate, a parallel pn layer in which regions of a first conductivity type and regions of a second conductivity type are disposed repeatedly alternating with each other. The semiconductor device further includes a third semiconductor region of the second conductivity type, configuring a voltage withstanding structure, in the termination region. Each of the regions of the second conductivity type includes multiple sub-regions stacked on one another, the multiple sub-regions including a topmost subregion that is closest to a first main surface of the semiconductor substrate. The third semiconductor region is formed at least partially by the plurality of topmost sub-regions in the termination region.

Abstract: A silicon carbide semiconductor device, including: a semiconductor substrate; a parallel pn layer, a first semiconductor region, a plurality of second semiconductor regions, and a plurality of third semiconductor regions formed in the semiconductor substrate; a plurality of gate trenches penetrating through the first to third semiconductor regions; and a plurality of first high concentration regions. The silicon carbide semiconductor device has a double gate structure in which, for each adjacent two gate trenches, a channel is formed over an entire area of a portion of the first semiconductor region therebetween, and is sandwiched by the adjacent two gate trenches. Each first-conductivity-type region of the PN layer has a width greater than a width of each first high concentration region. Each second-conductivity-type region has a width smaller than that of each portion of the first high concentration region and greater than a distance between any adjacent two gate trenches.

Abstract: A power supply circuit configured to generate an output voltage at a target level from an input voltage thereof. The power supply circuit includes a wiring configured to receive the input voltage, a variable resistor provided between the wiring and a predetermined node, a voltage generation circuit configured to apply a voltage at a predetermined level to the predetermined node based on a current from the variable resistor, an output circuit configured to output the output voltage at the target level, in response to the voltage at the predetermined level being applied to the predetermined node, and an adjustment circuit configured to increase a resistance value of the variable resistor in response to a predetermined time period having elapsed since starting of generation of the output voltage.

Abstract: In an intermediate region surrounding a periphery of an active region, a gate polysilicon wiring layer is provided on a gate insulating film at a front surface of a semiconductor substrate, via a field oxide film. An inner end portion of the gate polysilicon wiring layer faces a p-type region of a surface region at the front surface of the semiconductor substrate, via only the gate insulating film. In the intermediate region, at corners thereof facing corners of the active region, a low carrier lifetime region containing a carrier lifetime killer is provided so as to overlap the p-regions and, in a depth direction, face the gate polysilicon wiring layer, whereby the lifetime of the minority carriers of the corner portions of the intermediate region is shorter than the lifetime of the minority carriers of linear portions of the intermediate region.

Abstract: A semiconductor device has an active area in which a main current flows and an outer-edge area surrounding the active area. The semiconductor device includes: an n-type semiconductor layer made of a wide bandgap semiconductor; a plurality of p-type guard rings provided inside the semiconductor layer in the outer-edge area to surround the active area; and a separation region provided in a concentric ring shape in the outer-edge area to be in contact with both of the adjacent guard rings, wherein the separation region contains both n-type first impurities and p-type second impurities.

Abstract: A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.

Abstract: A semiconductor module has a stacked substrate, a semiconductor device mounted to the stacked substrate, a lead frame in contact with and electrically connecting the semiconductor device and a conductive plate on the stacked substrate, and an encapsulation resin that encapsulates encapsulated members, which include the semiconductor device, the lead frame, and the stacked substrate. The lead frame is configured by a Cu layer and an Al layer, the Cu layer being provided facing the semiconductor device and the Al layer being provided facing the encapsulation resin.

Abstract: A resin composition including a lignin skeleton capable of producing a heat-resistant molded article and being decomposed under relatively mild conditions. The resin composition contains a lignin skeleton including, as a base component, a phenolated lignin or a derivative thereof that contains a reactive monomer group, the phenolated lignin containing a phenol-containing monomer represented by the following general formula (I): wherein R1 to R5 are each independently a monovalent group selected from H, OH, a C1 to C6 alkyl group, a C1 to C6 alkoxy group, and a C6to C10 aryl group, or adjacent substituents among R1 to R5 form a substituted or unsubstituted aromatic ring together, at least one of R1 and R2 is a hydroxyl group, and R6 is OCH3 or H; a molded article thereof, as well as a recycling method for a molded article formed in a mold formed of the resin composition.

Abstract: A semiconductor device comprising a semiconductor substrate having upper and lower surfaces and a hydrogen containing region containing hydrogen and a lifetime control region is provided. The carrier concentration distribution of the hydrogen containing region has: a first local maximum point; a second local maximum point closest to the first local maximum point among local maximum points positioned between the first local maximum point and the upper surface; a first intermediate point of the local minimum between the first and second local maximum points; and a second intermediate point closest to the second local maximum point among local minimum points or flat points where the carrier concentration remains constant positioned between the second local maximum point and the upper surface. The lifetime control region is positioned at least between the first and second local maximum points. The first intermediate point has a lower carrier concentration than the second intermediate point.

Abstract: Provided is a semiconductor device comprising: a semiconductor substrate provided with a drift region; a buffer region arranged between the drift region and the lower surface, wherein a doping concentration distribution has three or more concentration peaks; and a collector region arranged between the buffer region and the lower surface, wherein the three or more concentration peaks in the buffer region include: a first concentration peak closest to the lower surface; a second concentration peak closest, next to the first concentration peak, to the lower surface, arranged 5 ?m or more distant from the lower surface in the depth direction, and having a doping concentration lower than the first concentration peak, the doping concentration being less than 1.0×1015/cm3; and a high concentration peak arranged farther from the lower surface than the second concentration peak, and having a higher doping concentration than the second concentration peak.

Abstract: A semiconductor device, including: a semiconductor substrate containing silicon carbide, the semiconductor substrate having a first main surface and a second main surface opposite to each other; an n-type region provided in the semiconductor substrate; a p-type region provided in the semiconductor substrate, between the first main surface of the semiconductor substrate and n-type region, the p-type region being in contact with the n-type region; a first electrode electrically connected to the p-type region; and a second electrode electrically connected to the n-type region. At least one portion of the p-type region is a p-type polysilicon portion.

Abstract: A semiconductor device includes an active region, a first-conductivity-type region, and a termination region. The active region has first second-conductivity-type regions, silicide films, and a first electrode; the termination region has a second second-conductivity-type region. The active region is configured by ohmic regions where the first electrode is in contact with the silicide films, and Schottky regions where the first electrode is in contact with the first-conductivity-type region. When a doping concentration of the first-conductivity-type region is a low concentration, a greater number of the ohmic regions is provided in a chip center portion than in a chip outer peripheral portion and when the doping concentration of the first-conductivity-type region is a high concentration, a greater number of the ohmic regions is provided in the chip outer peripheral portion than in the chip center portion.

Abstract: A semiconductor device includes a circuit substrate having a semiconductor element thereon, a case surrounding a periphery of the circuit substrate so as to house the circuit substrate therein, and a lid disposed above the circuit substrate so as to close the case at an upper side thereof. The lid includes a plurality of extending portions including a first extending portion and a second extending portion, and a plurality of deformation holes respectively provided for one of the plurality of extending portions. The plurality of extending portions each extend from a lower surface of the lid facing the circuit substrate toward the circuit substrate and have a protrusion at an end thereof. The protrusion of the first extending portion protrudes in a first direction and the protrusion of the second extending portion protrudes in a second direction opposite to the first direction.

Abstract: A semiconductor device includes: a wiring layer; a titanium nitride layer deposited on the wiring layer; a titanium oxynitride layer deposited on the titanium nitride layer; a titanium oxide layer deposited on the titanium oxynitride layer; and a surface passivation film deposited on the titanium oxide layer, wherein an opening penetrating the titanium nitride layer, the titanium oxynitride layer, the titanium oxide layer, and the surface passivation film is provided to expose a part of the wiring layer so as to serve as a pad.