Abstract: Aspects of the invention are related to a semiconductor device including a first conductivity type n-type drift layer, a second conductivity type VLD region which is formed on a chip inner circumferential side of a termination structure region provided on one principal surface of the n-type drift layer and which is higher in concentration than the n-type drift layer, and a second conductivity type first clip layer which is formed on a chip outer circumferential side of the VLD region so as to be separated from the VLD region and which is higher in concentration than the n-type drift layer. The invention can also include a first conductivity type channel stopper layer which is formed on a chip outer circumferential side of the first clip layer so as to be separated from the first clip layer and which is higher in concentration than the n-type drift layer.

Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.

Abstract: A photovoltaic module has a photovoltaic cell assembly and a diode assembly. The photovoltaic cell assembly is formed by stacking a rear surface electrode layer, a photoelectric conversion layer, and a transparent electrode layer on one surface of a substrate, and an electrode layer formed on the other surface of the substrate. The diode assembly is formed by sequentially stacking a first electrode layer, a semiconductor layer, and a second electrode layer on one surface of a second substrate. The first electrode layer or the second electrode layer of the diode assembly is formed of a conductive oxide. The electrode layer formed on the other surface of the substrate of the photovoltaic cell assembly and the electrode layer of the diode assembly surface-contact and electrically connected with each other. The photovoltaic cell assembly and the diode assembly are sealed and integrated with each other by a sealing member.

Abstract: A comparator comprises a differential amplifier type including input MOSFETs receiving differential input of a reference voltage and an input voltage, load MOSFETs for the input MOSFETs, and a constant current source to supply the sources of the input MOSFETs. The comparator comprises a Zener diode that is connected between the gate and source of the input MOSFETs and exhibits a breakdown voltage lower than the withstand voltage of the gate oxide film of the input MOSFET. Another comparator further comprises a feedback MOSFET that performs negative feedback of an output voltage of a main body comparator to the gates of the load MOSFETs to restrict the amplitude of the output voltage. Still another comparator further comprises a semiconductor rectifying element that exhibits a reverse-blocking characteristic higher than the power supply voltage and is interposed between the constant current source and the source of each of the input MOSFETs.

Abstract: A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers.

Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.

Abstract: A highly-reliable gate driving circuit achieved by suppressing the amount of hot-carriers generated in a MOSFET. In the gate driving circuit having NOEMI circuits, same-type NOEMI circuits are connected in series with a p-channel MOSFET constituting a gate charging circuit and an n-channel MOSFET constituting a gate discharging circuit, respectively, so as to suppress the amount of hot-carriers generated in the p-channel MOSFET and the n-channel MOSFET.

Abstract: A distributed power supply system in which no simultaneous disconnection from the system occurs when a system voltage momentarily drops is provided. It includes an inverter circuit that converts a direct current power generated by a direct current power supply and that supplies the alternating current power to an alternating current power supply power system, and an inverter control circuit for carrying out PWM control of the inverter circuit, wherein the inverter control circuit includes a three-phase voltage command signal generation unit, that is configured of a three-phase fundamental wave signal generation unit that generates three-phase fundamental wave signals from two phase components of voltage detected by a voltage detector, and a third harmonic signal generation unit that adds together third harmonic components of respective phases, having a predetermined amplitude, generated based on the three-phase fundamental wave signals.

Abstract: A gate driving circuit for driving an insulated gate switching element, including a gate charging circuit configured to charge gate capacitance of the insulated gate switching element, and a gate discharging circuit that is connected in series with the gate charging circuit and configured to discharge a charge of the gate capacitance. The gate charging circuit includes a first p-channel metal oxide semiconductor field effect transistor (MOSFET), and a first hybrid normally-on enhancement MOSFET insertion (NOEMI) circuit connected in series with a drain of the first p-channel MOSFET. The gate discharging circuit includes a first n-channel MOSFET, and a second hybrid NOEMI circuit connected in series with a drain of the first n-channel MOSFET.

Abstract: A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

Abstract: An electrophotographic photoreceptor includes an electroconductive substrate; an undercoat layer provided on the electroconductive substrate and composed of: metal oxide fine particles including particles of at least one metal oxide and at least one organic compound provided on the particles of the at least one metal oxide as a surface treatment; and a copolymer resin synthesized by copolymerization of essential constituent monomers composed of a dicarboxylic acid, a diol, a triol and a diamine; and a photosensitive layer laminated on the undercoat layer. The undercoat layer permits (a) attaining stable electric potential characteristics in all environments ranging from low temperature and low humidity environments to high temperature and high humidity environments, (b) suppressing the occurrence of printing defects and density differences, and (c) simultaneously attaining transfer restorability and restorability from intense light-induced fatigue even in a wide variety of usages and operation environments.

Abstract: A superjunction semiconductor device is disclosed which has, in the active section, a first alternating-conductivity-type layer which makes a current flow in the ON-state of the device and sustains a bias voltage in the OFF-state of the device. There is a second alternating-conductivity-type layer in a edge-termination section surrounding the active section. The width of a region of a second conductivity type in the second alternating-conductivity-type layer becomes narrower at a predetermined rate from the edge on the active section side toward the edge of the edge termination section. The superjunction semiconductor device facilitates manufacturing the edge-termination section which exhibits a high breakdown voltage and a high reliability for breakdown voltage through a process that exhibits a high mass-productivity.

Abstract: A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench 10p. In this manner, there is provided a trench gate type semiconductor device and a method of producing the same, in which: the cell pitch can be reduced even when a wide band gap semiconductor is used as a main semiconductor substrate; good ohmic contacts can be obtained; and an excessive electric field is prevented from being applied to an insulating film in the bottom of each trench.

Abstract: In relation to a multilevel inverter of three levels or more, a decrease in safety due to breakdown is suppressed while avoiding destruction of switching elements. An inverter includes switching elements connected in series between a positive terminal and a negative terminal, reverse blocking switching elements connected one each between connection points of pairs of the switching elements and an intermediate terminal, alternating current output terminals, a control unit that generates control signals for switching between a turning on and turning off of the plurality of switching elements, a control signal interrupt circuit that, on an interrupt signal interrupting the output voltage of the alternating current output terminals being input, interrupts each of the control signals to the first switching elements and second switching elements, regardless of the state of the control signals, and a monitoring unit that diagnoses a breakdown of the control signal interrupt circuit.

Abstract: A transport cart for conveying an inverter stack to a switchboard in which the inverter stack is to be installed and for installing the inverter stack into the switchboard, includes a support surface having a same height level as inverter stack mounting surfaces in the switchboard and supporting the inverter stack in a mounted condition; and a projecting portion disposed to protrude outward from the support surface and for entering an entrance portion formed between the mounting surfaces to carry out positioning in a horizontal direction.

Abstract: Provide is an etching completion detection method that accurately detects an etching completion position in an SOI substrate, regardless of the width of an opening. This etching completion detection method is a method for detecting etching completion when a silicon layer is being etched to form an opening that reaches an insulating layer in an SOI substrate in which the silicon layer is disposed on the insulating layer, the method including: forming a first electrode layer on a surface of an islet region that is surrounded by a loop-shaped opening to be formed by the etching, and a second electrode layer in a region outside the stripe region; measuring an electrical resistance between the first electrode layer and the second electrode layer; and determining that the loop-shaped opening has reached an etching completion position when the electrical resistance exceeds a preset threshold.

Abstract: An electrophotographic photoreceptor is used by being detachably mounted onto an apparatus main body of an electrophotographic application apparatus while being incorporated in a process cartridge. The electrophotographic photoreceptor has a photosensitive drum formed by forming a photosensitive layer containing a photoconductive material on an outer circumferential surface of a cylindrical conductive substrate; and a flange that is fitted to an open end of the photosensitive drum and transmits a rotational driving force from the apparatus main body to the photosensitive drum. In the flange, on a surface thereof receiving the rotational driving force, a driven-side power transmission portion that is configured by a cylindrical body disposed concentrically with respect to a central shaft of the photosensitive drum, and engaging projections are provided.

Abstract: An inverter device includes an inverter stack, and a switchboard to insert the inverter stack from a front side to store. The inverter stack, as an output relay unit, linking three phase output terminals and output relay terminals forming the switchboard, alternatively, selects a first output relay unit wherein three phase output relay bars for directly outputting three phases of outputs from the output terminals to the output relay terminals and a fixing plate to fix the three phase output relay bars to the inverter stack are unitized through an insulating member, or a second output relay unit wherein a single-phase output relay bar for outputting three phase outputs from the output terminals as a single phase to the output relay terminals and a fixing plate to fix the single-phase output relay bar to the inverter stack are unitized through an insulating member.