Patents Assigned to Fuji Electric Co., Ltds.
  • Publication number: 20240137015
    Abstract: A semiconductor module, including: a first circuit board and a second circuit board respectively have a first switching element and a second switching element located thereon, each of the first and second switching elements having an emitter electrode; a first connecting portion and a second connecting portion respectively electrically connected to the emitter electrodes of the first and second switching elements over the first and second circuit boards; an auxiliary emitter terminal; and an auxiliary emitter wiring electrically connected to the auxiliary emitter terminal. The auxiliary emitter wiring includes: a branch point, a common wiring portion which connects the auxiliary emitter terminal and the branch point, and a first discrete wiring portion and a second discrete wiring portion which connect the branch point respectively to the first and second connecting portions, and which each have an inductance smaller than 10 percent of an inductance of the common wiring portion.
    Type: Application
    Filed: August 21, 2023
    Publication date: April 25, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Norihiro KOMIYAMA, Masahiro SASAKI
  • Publication number: 20240136319
    Abstract: A semiconductor module includes a circuit board having a semiconductor element mounted thereon, a lead including a first bonding portion bonded to the semiconductor element via a bonding material and a wiring portion connected to the first bonding portion, and a sealing material that seals the semiconductor element and the lead. The first bonding portion has first and second side surfaces that face each other. The wiring portion has a bent portion connected to the first bonding portion at a side of the first bonding portion at which the first side surface is located. The bent portion is bent at a border between the first bonding portion and the bent portion in a direction away from a lower surface of the first bonding portion. The border is located between the first and second side surfaces of the first bonding portion in a plan view of the lead.
    Type: Application
    Filed: August 23, 2023
    Publication date: April 25, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Mai SAITO, Daiki YOSHIDA
  • Publication number: 20240136940
    Abstract: A control circuit for a circuit that has a rectifier circuit including first to fourth diodes, and first to fourth switches respectively connected in parallel with the first to fourth diodes, for rectifying an AC voltage; and a capacitor receiving the rectified AC voltage. The control circuit controls the first to fourth switches, and includes: a determination unit determining an off-period in which, when the AC voltage is applied, the first to fourth diodes turn off, the off-period including a first period and a second period, in which the first and fourth diodes, and the second and third diodes, respectively turn off; and a control unit turning on the first and fourth switches in the first period, when the second and third diodes are off, and turning on the second and third switches in the second period, when the first and fourth diodes are off.
    Type: Application
    Filed: August 21, 2023
    Publication date: April 25, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Hironobu SHIROYAMA
  • Publication number: 20240128266
    Abstract: A semiconductor device includes: a semiconductor base body of a first conductivity-type; a first well region of a second conductivity-type provided in the semiconductor base body; at least one second well region of the first conductivity-type implementing a part of a high-side circuit provided in the first well region; a buried layer of the second conductivity-type provided at a bottom of the first well region and having a higher impurity concentration than the first well region; a voltage blocking region of the second conductivity-type provided at a circumference of the first well region; and an extraction region of the first conductivity-type provided to have a greater depth than the second well region at least at a part of a circumference of the high-side circuit in the first well region so as to be opposed to the second well region.
    Type: Application
    Filed: August 28, 2023
    Publication date: April 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Akihiro JONISHI
  • Publication number: 20240128965
    Abstract: A semiconductor module 1 includes an IGBT 31z configured to supply a motor 24 with power, a pre-driver 41z configured to drive the IGBT 31z, a protection unit 42z configured to execute first protection operation protecting the IGBT 31z and the pre-driver 41z from operation in an abnormal state, an IGBT 31db configured to adjust the magnitude of voltage input to the IGBT 31z, a pre-driver 41db configured to drive the IGBT 31db, and a protection unit 42db configured to execute second protection operation protecting the IGBT 31db from operation in an abnormal state, and the protection unit 42db executes the second protection operation when the IGBT 31db is operating in an abnormal state and otherwise does not execute the second protection operation regardless of whether or not the protection unit 42z is executing the first protection operation.
    Type: Application
    Filed: August 23, 2023
    Publication date: April 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Eiji KUROSAWA
  • Publication number: 20240128350
    Abstract: A method of manufacturing a semiconductor device, including: preparing a semiconductor substrate; forming a first semiconductor layer at a first main surface of the semiconductor substrate; forming and etching an oxide film to form a trench mask; using the trench mask to form a plurality of trenches penetrating through the first semiconductor layer; forming a plurality of gate insulating films along the surface of the first semiconductor layer and bottoms and sidewalls of the plurality of trenches; forming a polycrystalline silicon layer on the plurality of gate insulating films; etching the polycrystalline silicon layer to form a plurality of gate electrodes; selectively forming a plurality of first semiconductor regions in the first semiconductor layer; forming a first electrode at the surface of the first semiconductor layer and on the plurality of first semiconductor regions; and forming a second electrode at a second main surface of the semiconductor substrate.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Seiji NOGUCHI
  • Publication number: 20240128241
    Abstract: A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; and an external connection terminal electrically connected to the semiconductor chip and including an inner-side conductor layer, an outer-side conductor layer provided at a circumference of the inner-side conductor layer, and an insulating layer interposed between the inner-side conductor layer and the outer-side conductor layer.
    Type: Application
    Filed: August 23, 2023
    Publication date: April 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akira HIRAO, Yoshinari IKEDA, Motohito HORI
  • Patent number: 11958508
    Abstract: A control system for an electrically-operated railroad car end door includes, an actuator, a processor, and a memory storing program instructions that cause the processor to instruct the actuator to begin generating a braking force applied to the railroad car end door in response to an opening of the railroad car end door, and determine whether the railroad car end door is being manually opened by a person based on information related to a state of the railroad car end door while the braking force is being generated.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: April 16, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Satoru Ozaki
  • Publication number: 20240120249
    Abstract: [Problem] An object of the present invention is to provide a semiconductor module capable of preventing a wire wiring from being broken because of a crack having occurred in sealing resin. [Solution] A semiconductor module 1 includes semiconductor chips 14a to 14d, sealing resin 18 configured to seal the semiconductor chips 14a to 14d, a case 11 including a casting area 117u, first portions 111 and 112, and second portions 113 and 114, wire wirings 101a to 101j and 102a to 102i sealed in the sealing resin 18 while being located closer to the first portion 111 and connected to the semiconductor chips 14a to 14d, and recessed portions 131a, 131b, 132a, and 132b formed on the second portions 113 and 114 between a virtual surface VSu and the first portion 112.
    Type: Application
    Filed: August 29, 2023
    Publication date: April 11, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato NAKANO
  • Patent number: 11955540
    Abstract: Provided is a semiconductor device, comprising a semiconductor substrate; and an emitter electrode provided above an upper surface of the semiconductor substrate; wherein the semiconductor substrate has: a first conductive type drift region; a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate; a second conductive type contact region with a higher doping concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate; a trench contact of a conductive material provided to connect to the emitter electrode and penetrate the contact region; and a second conductive type high-concentration plug region with a higher doping concentration than the contact region, which is provided in contact with a bottom portion of the trench contact.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Patent number: 11955791
    Abstract: A short-circuit detector includes: a first Rogowski coil configured to generate a first detection signal in accordance with a current that flows through a first arm due to a short circuit in a load; a second Rogowski coil configured to generate a second detection signal in accordance with a current that flows through the first arm due to a short circuit in the first arm or a second arm; a load short-circuit detection circuit configured to detect the short circuit in the load, based on the first detection signal; an arm short-circuit detection circuit configured to detect the short circuit in the first arm or the second arm, based on the second detection signal; and a short-circuit detection circuit configured to detect a short-circuit, based on: an output signal output from the load short-circuit detection circuit; and an output signal output from the arm short-circuit detection circuit.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Natsuko Takeuchi, Kunio Matsubara, Hiromu Takubo
  • Patent number: 11955398
    Abstract: A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Eri Ogawa
  • Publication number: 20240113628
    Abstract: An integrated circuit for a power supply circuit that generates an output voltage, and that includes: a transformer including primary and secondary coils, first and second transistors controlling a current of the primary coil, and a resonant circuit including the primary coil and a first capacitor. The integrated circuit controls the first and second transistors. The integrated circuit includes: a voltage generator circuit supplying a first current to a second capacitor, and to generate a first voltage at the second capacitor; a driving signal output circuit outputting a driving signal for driving the first and second transistors, based on the first voltage and a feedback voltage corresponding to the output voltage; and a control circuit controlling the voltage generator circuit such that, when the output voltage drops and a derivative of the feedback voltage at a time point is greater than a predetermined value, the first current increases and then decreases.
    Type: Application
    Filed: August 22, 2023
    Publication date: April 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshizawa TSUYOSHI
  • Publication number: 20240109157
    Abstract: In an example, use of a solder joint may include a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface of the joined body in contact with the solder joint layer. The Ni—P—Cu plating layer may contain Ni as a main component and may contain 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, and the Ni—P—Cu plating layer may have a microcrystalline layer at an interface with the solder joint layer.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko WATANABE, Shunsuke SAITO, Takeshi YOKOYAMA
  • Publication number: 20240112991
    Abstract: A semiconductor module includes: a stacked substrate; a semiconductor element arranged on an upper surface of the first circuit board; a metal wiring board including a first bonding portion bonded to an upper surface of the semiconductor element with a bonding material; and a sealing resin that seals the stacked substrate, the semiconductor element, and the metal wiring board. The first bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The metal wiring board has a first standing portion standing up from one end of the first bonding portion, and a second standing portion standing up from the other end of the first bonding portion. The first standing portion constitutes a part of a wiring path through which a main current flows. The second standing portion constitutes a non-wiring path through which the main current does not flow.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Mai SAITO, Yoko NAKAMURA
  • Patent number: 11949347
    Abstract: A power conversion device includes a power converter to output AC power by converting input DC power, an electric leakage detector to detect electric leakage in a power supply line through which the AC power output by the power converter flows when the AC power is being output by the power converter, and a power conversion controller configured to control power conversion of the power converter. The power conversion controller is configured to stop power conversion operation of the power converter based on a detection result of the electric leakage detector.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignees: FUJI ELECTRIC CO., LTD., HONDA MOTOR CO., LTD.
    Inventors: Nobuhisa Ando, Hiroki Katsumata, Masahiko Sato
  • Patent number: 11949005
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Takahashi, Yuichi Harada, Kouta Yokoyama
  • Patent number: 11949338
    Abstract: A power converter includes a positive busbar electrically connected to a positive terminal and the first capacitor electrode, and includes a negative busbar electrically connected to a negative terminal and the second capacitor electrode. The power converter includes output busbars each electrically connected to a given output terminal among multiple output terminals, a given high-side switching element among a plurality of high-side switching elements, and a given low-side switching element among a plurality of low-side switching elements. The power converter includes a cooler that cools the high-side switching elements and the low-side switching elements. The power converter includes a housing that accommodates a supply tube and a discharge tube. The positive terminal, the negative terminal, the output terminals, the inlet port, and the outlet port are exposed on the housing. The inlet port, the outlet port, the supply tube, and the discharge tube are separate members from the housing.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuji Suzuki, Motohito Hori, Akio Toba, Ikuya Sato, Yasuhito Tanaka, Masamichi Iwasaki, Masaaki Ajima, Nobuaki Ohguri
  • Patent number: 11948937
    Abstract: A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity-type; a bottom surface electrode to which a first potential is applied, the bottom surface electrode being provided on a bottom surface of the semiconductor base body; a first well of a second conductivity-type to which a second potential lower than the first potential is applied, the first well being provided on a top surface side of the semiconductor base body; a second well of the first conductivity-type provided in the first well; and an edge structure provided in the first well and configured to supply a third potential higher than the second potential to the second well.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki Toyoda
  • Patent number: 11948976
    Abstract: A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Koichi Murata