Abstract: A semiconductor device includes an integrated circuit having a first resistor configuring a voltage divider circuit, a sensing resistor configured to measure a sheet resistance having a same attribute as that of the first resistor, a temperature detection circuit configured to detect a value of a first temperature, a storage circuit configured to store a table including first information for each of a plurality of values of the first temperatures, the first information corresponding to a sheet resistance of the first resistor obtained based on a result of measurement of the sensing resistor, and indicating a relationship between a second temperature and a divided voltage of the voltage divider circuit at the second temperature, and an arithmetic circuit configured to obtain the second temperature, based on the first information at the value of the first temperature detected by the temperature detection circuit and the divided voltage.

Abstract: A gate insulating film has a multilayer structure including a SiO2 film, a LaAlO3 film, and an Al2O3 film that are sequentially stacked, relative permittivity of the gate insulating film being optimized by the LaAlO3 film. In forming the LaAlO3 film constituting the gate insulating film, a La2O3 film and an Al2O3 film are alternately deposited repeatedly using an ALD method. The La2O3 film is deposited first, whereby during a POA performed thereafter, a sub-oxide of the surface of the SiO2 film is removed by a cleaning effect of lanthanum atoms in the La2O3 film. A temperature of the POA is suitably set in a range from 700 degrees C. to less than 900 degrees C.

Abstract: A semiconductor device including a semiconductor chip, an insulating circuit board having a circuit pattern formed on an insulating plate, a case including a frame part having an opening that is substantially rectangular in a plan view of the semiconductor device, inner wall surfaces of the frame part at the opening forming a storage part to store the insulating circuit board, and a printed circuit board which has a flat plate shape and which protrudes from one of the inner wall surfaces of the frame part toward the storage part. The semiconductor device further includes a sealing material filled in the storage part, to thereby seal the semiconductor chip and the printed circuit board. A front surface of the sealing material forms a sealing surface, and in a thickness direction of the semiconductor chip, the sealing surface is higher around the printed circuit board than around the semiconductor chip.

Abstract: A semiconductor module circuit structure, including an insulating circuit substrate having an insulating plate, and a circuit pattern formed on a top face of the insulating plate, and a semiconductor element disposed on a top face of the circuit pattern. The circuit pattern includes a first straight part extending in a first direction, a second straight part extending in a second direction different from the first direction, and a corner part connecting the first and second straight parts. A wiring member is formed on a top surface of the first straight part along the first direction, the wiring member being formed off-center at the first straight part to be closer to an outer periphery of the circuit pattern.

Abstract: There is provided a semiconductor device including a drift region of a first conductivity type, a first semiconductor region of the first conductivity type provided above the drift region and having a doping concentration higher than the drift region, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the drift region, and a plurality of trench portions arranged in a first direction and having an extending portion that extends in a second direction perpendicular to the first direction. At least one trench portion of the plurality of trench portions has a first tapered portion at an upper side than a depth position of a lower surface of the second semiconductor region. The width of the first tapered portion in the first direction becomes smaller from a lower side of the first tapered portion toward an upper side of the first tapered portion.

Abstract: A control circuit for controlling an output transistor for outputting power includes: a ramp terminal connected to a ramp resistance; a ramp waveform generation unit for generating a ramp waveform including a slope corresponding to a resistance value of the ramp resistance; an output control unit for controlling at least one of an ON time or an OFF time of the output transistor based on a comparison result between the ramp waveform and a comparison voltage; and a state detection unit for detecting a state of the ramp resistance connected to the ramp terminal, wherein the output control unit turns the output transistor to an OFF state regardless of the comparison result, when the state of the ramp resistance becomes a predetermined state.

Abstract: Even when a fault occurs on an electric power system, a command signal based on appropriate calculation is given to a distributed power supply. Provided is a control apparatus configured to control a plurality of distributed power supplies connected to an electric power system. The control apparatus comprises: a first calculation unit configured to calculate in advance reactive electric power to be output by each of the distributed power supplies in the event of a fault on the electric power system; and a command output unit configured to output, to each of the distributed power supplies, a command signal for causing each of the distributed power supplies to output the reactive electric power calculated in advance by the first calculation unit when it is detected that a fault has occurred on the electric power system.

Abstract: A semiconductor device includes an output-stage element and a detection element, each of the output-stage element and the detection element including: a channel-formation region deposited at an upper part of a drift region; a main electrode region deposited at an upper part of the channel-formation region; and a gate electrode buried via a gate insulating film in one or more first trenches in contact with the main electrode region, the channel-formation region, and the drift region, wherein the first trenches used in common with the detection element and the output-stage element extend in a planar pattern, and a plurality of second trenches extending in parallel to each other in a direction perpendicular to the first trenches interpose the detection element so as to separate the channel-formation region of the output-stage element and the channel-formation region of the detection element from each other.

Abstract: A semiconductor device includes a semiconductor chip having a main electrode on a front surface thereof, a wiring board having a front surface to which a rear surface of the semiconductor chip is bonded, a sealing member sealing the wiring board and the semiconductor chip, and an adhesive layer including at least two adhesive films that are laminated to each other. The adhesive layer is provided on surfaces of the wiring board and the semiconductor chip so that the sealing member seals the wiring board and the semiconductor chip via the adhesive layer. As a result, the sealing member is able to reliably seal the semiconductor chip and wiring board via the adhesive layer, thereby preventing an occurrence and extension of separation.

Abstract: A switching control circuit for a power supply circuit that includes an inductor to which a voltage in accordance with an alternating current (AC) voltage is applied, and a transistor controlling an inductor current flowing through the inductor, the power supply circuit generating an output voltage from the AC voltage, the switching control circuit being configured to control switching of the transistor, the switching control circuit comprising: an ON signal output circuit that outputs an ON signal to turn on the transistor in response to the inductor current reaches a predetermined current, when a feedback voltage in accordance with the output voltage indicates that the output voltage is lower than a first level, and outputs the ON signal every first cycle when the feedback voltage indicates that the output voltage is higher than the first level; an OFF signal output circuit that outputs an OFF signal to turn off the transistor based on the feedback voltage; and a driver circuit that drives the transistor ba

Abstract: A semiconductor device includes: a resin insulated substrate including a first rein insulating layer, a conductor base provided on one of main surfaces of the first resin insulating layer, and a conductor foil provided on another main surface of the first resin insulating layer; a power semiconductor element bonded to the conductor foil; a case surrounding an outer circumference of the resin insulated substrate; a sealing resin provided inside the case to seal the power semiconductor element; and a second resin insulating layer provided between the first resin insulating layer and the sealing resin and having a lower water-absorption rate than the sealing resin.

Abstract: A method of manufacturing a semiconductor device includes: forming a first trench from an upper surface side of a semiconductor substrate; burying the first trench with an insulated gate electrode structure; forming a base region at an upper part of the semiconductor substrate so as to be in contact with the first trench; forming a first main electrode region at an upper part of the base region so as to be in contact with the first trench; forming a second trench by removing a part of the first main electrode region; implanting first impurity ions entirely into a side wall surface of the second trench from a diagonally upper side; implanting second impurity ions into a bottom surface of the second trench to form a contact region at a bottom of the second trench; and forming a second main electrode region on a bottom surface side of the semiconductor substrate.

Abstract: A switching control circuit for a power factor correction circuit configured to generate an output voltage from an alternating current (AC) voltage, the power factor correction circuit including an inductor configured to receive a rectified voltage corresponding to the AC voltage, and a transistor configured to control an inductor current flowing through the inductor. The switching control circuit is configured to control switching of the transistor. The switching control circuit includes: a driving signal output circuit configured to, when a peak value of the inductor current in a half cycle of the AC voltage is smaller than and greater than a first predetermined value, output a driving signal to operate the power factor correction circuit in a critical mode and in a continuous mode, respectively; and a driver circuit configured to drive the transistor, in response to the driving signal.

Abstract: A semiconductor module includes an insulated circuit substrate including a semiconductor chip, an insulated circuit substrate including a wiring board provided on a front surface thereof, the wiring board having the semiconductor chip bonded thereto, a heat dissipation base having a front surface and a rear surface opposite to each other. The front surface has a substrate region to which the insulated circuit substrate is bonded. The rear surface has a heat dissipation region positioned overlapping the substrate region in a plan view of the semiconductor module and a loop-shaped region surrounding the heat dissipation region. The semiconductor module further includes a solid heat dissipation member made of a phase change material and provided on the rear surface of the heat dissipation base in the heat dissipation region, and an elastic member provided on the rear surface of the heat dissipation base in the loop-shaped region.

Abstract: A semiconductor device includes: an insulated gate electrode structure provided in a semiconductor substrate; a base region; a first main electrode region; a contact plug buried in a trench penetrating the first main electrode region to reach the base region with a barrier metal film interposed; an interlayer insulating film provided with a contact hole integrally connected to the trench; a contact region provided in contact with a bottom of the trench; and a second main electrode region, wherein an opening width at a lower end of the contact hole conforms to a width at an opening of the trench, an upper part of a side wall continued from the opening of the trench has a curved surface convex to an outside, and a lower part of the side wall continuously connected to the bottom of the trench has a curved surface convex to the outside.

Abstract: A power converter includes a housing including a convex radiator that radiates heat from a heater element and protrudes toward a board, in which the board and the heater element are arranged, and an urging member that is arranged between the board and a bottom surface of the housing and urges the heater element toward a first side surface of the convex radiator of the housing.

Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a low-concentration semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a semiconductor layer of the second conductivity type in the active region and a semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the semiconductor layer, and the second semiconductor layer is not in contact with a surface of the semiconductor substrate.

Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; first semiconductor regions of the first conductivity type; trenches; gate insulating films; gate electrodes; first high-concentration regions of the second conductivity type provided at positions facing the trenches in a depth direction; second high-concentration regions of the second conductivity type, selectively provided between the trenches and in contact with the first semiconductor regions, each having an upper surface exposed at the surface of the second semiconductor layer and a lower surface partially in contact with upper surfaces of the first high-concentration regions; a first electrode; and a second electrode. The second high-concentration regions are disposed periodically in a longitudinal direction of the trenches.

Abstract: A p++-type outer peripheral contact region is provided in an edge termination region and surrounds a periphery of an active region in a rectangular shape having rounded corners, in a plan view. The p++-type outer peripheral contact region faces a gate runner on a front surface of a semiconductor substrate via an insulating layer. In the active region, a p++-type region is provided facing a gate pad on the front surface of the semiconductor substrate via the insulating layer. The p++-type outer peripheral contact region and the p++-type region are provided apart from p++-type contact regions that form source contacts with a source electrode. The p++-type contact regions and contact holes in which the source contacts are formed are disposed in a uniform layout spanning an entire area of the active region so that an end side and a center side of the active region have the same layout.

Abstract: A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.