Abstract: A system for mapping tasks of at least one application on processing units of a reconfigurable array, the system comprising a plurality of programmable processing units, each programmable processing unit having at least one connection node, the programmable processing units disposed on a layer permitting interconnection between connection nodes; and a mapping unit adapted to substantially simultaneously optimize placement of the tasks on the plurality of programmable processing units and routing of interconnections between the plurality of processing units, the mapping unit adapted to select one placement algorithm among a plurality of predetermined placement algorithms and to select one routing algorithm from a plurality of predetermined placement algorithms, the selection configured to prefer use of non-random algorithms.

Abstract: Optical apparatuses providing optical interconnections among a plurality N of electronic components. One exemplary apparatus comprises a slab waveguide having a core layer that enables light beams to propagate in a plurality of directions, a plurality of N reception ports, and a plurality of N transmission ports, each reception port and each transmission port serving a respective electronic component, and each being optically coupled to the core layer of the slab waveguide. Each transmission port is configured to receive a plurality of light beams from its assigned electronic component and to transmit each received light beam onto the slab waveguide in a direction toward a reception port. Each reception port is configured to receive from the slab waveguide a plurality of light beams transmitted to it from at least two different transmission ports. Light beams within the slab waveguide are permitted to cross paths. Other exemplary embodiments are disclosed.

Abstract: Optical backplanes providing integrated optical couplers to external optical fibers are disclosed, along with methods for making the same. An exemplary optical backplane has a first cladding layer disposed over the top surface of a substrate, and at least a first core body disposed over the first cladding layer, with the first core body having a first end and a second end. A material layer is disposed above the first cladding layer and the first end of the first core body, with the material layer having a top surface and a bottom surface. A focusing element is formed at the top surface of the material layer, with the focusing element being located above the first end of the first core body.

Abstract: An information processing apparatus includes a TPM, a key management module for managing a key database, a memory, and a file processing module for encrypting and decrypting a file. The TPM stores a first TPM key therein and encrypts a third TPM key. The key management module stores and manages the third TPM key in the database. When the information processing apparatus starts communicating with the tamper-proof device, the key management module receives, from the TPM, a parameter for generating a second TPM key, provides the received parameter to the tamper-proof device, receives from the tamper-proof device the second TPM key which has been encrypted using the first TPM key, and provides the TPM with the second TPM key and with the third TPM key which has been encrypted using the second TPM key.

Abstract: A resin coating method for applying resin to a predetermined region of a wiring board includes the steps of imaging an external appearance of the resin extruded from a resin application device; and automatically adjusting an amount of the resin extruded from the resin application device based on the external appearance of the resin obtained in the imaging step.

Abstract: A resin coating method for applying resin to a predetermined region of a wiring board includes the steps of imaging an external appearance of the resin extruded from a resin application device; and automatically adjusting an amount of the resin extruded from the resin application device based on the external appearance of the resin obtained in the imaging step.

Abstract: A resin coating method for applying resin to a predetermined region of a wiring board includes the steps of imaging an external appearance of the resin extruded from a resin application device; and automatically adjusting an amount of the resin extruded from the resin application device based on the external appearance of the resin obtained in the imaging step.

Abstract: A multifan-equipped apparatus in which a plurality of objects mounted are controllably cooled by blowing air using a fan-unit assembly composed of a plurality of fan units. The plural fan units are divided into a plurality of groups; the fan units in the same group are arranged in a queue. And one of the fan units of each group is a master fan unit that is autonomically adjustable in revolutions per minute (rpm) in accordance with a current apparatus-environment temperature and serves to make a tuning control on the rpm of at least one of the remaining fan units in the same group so as to adjust the rpm to a first estimated value corresponding to the autonomic-adjusted rpm of the master fan unit.

Abstract: The present invention relates to a method for optical fiber communication, and a terminal device and system for use in carrying out the method, and an object of the present invention is to compensate for chromatic dispersion and nonlinearity. A device for outputting an optical signal having a variable optical power into an optical fiber transmission line is provided. The optical signal transmitted by the transmission line is converted into an electrical signal by an optical receiver. A parameter related to waveform degradation of the electrical signal is detected by a monitor unit. A control unit controls the optical power of the optical signal to be output from the device so that the waveform degradation is improved.

Abstract: In a multi-processor computer system, a message receive unit using a shared buffer pool and a set of per-node credit registers in each processor node. The buffer stores incoming messages received from the sending nodes. The credit registers prevent a sending node from using more than its allocated share of the buffer pool and thus prevent the buffer pool from overflowing. Because the buffer pool of the receiving node does not overflow, the receiving node can continue to communicate with other nodes.

Abstract: An optical demultiplexer to reduce the number of expensive dispersion compensators when compensating secondary dispersion during demultiplexing. By providing optical circulators, dispersion compensators, and optical filters that reflect specified wavelengths and transmit wavelengths other than the specified wavelengths from among the outputs of the dispersion compensators, and causing specified wavelengths to make round trips of the dispersion compensators, the dispersion volume of the dispersion compensators is reduced.

Abstract: A semiconductor memory device has a mask signal receiving circuit which receives a data mask signal, fed from an external unit, out of synchronism and produces an asynchronous internal mask signal. The semiconductor memory device includes a function for interrupting a reading of data during a burst output in response to the data mask signal. The reading of data during the burst output is interrupted by using the internal mask signal. Therefore, the operation time can be shortened when the burst reading is interrupted by a write processing, and thereby the efficiency for using the data bus can be enhanced and the operation can be executed at higher speeds.

Abstract: A storage medium stores information on a plurality of tracks formed thereon, each of the tracks being divided into a plurality of sectors. The storage medium includes a physically formed sector beginning identifier provided at a leading portion of each sector, and an information storing portion. The information storing portion, another sector address portion at the trailing end of the information storing portion, includes at least one sector address portion at a leading end of the information storing portion, another sector address portion at the trailing end of the information storing portion, and a data portion provided between the two sector address portions.

Abstract: An algorithm for selecting a directory entry in a multiprocessor-node system. In response to a memory request from a processor in a processor node, the algorithm finds an available entry to store information about the requested memory line. If at least one entry is available, then the algorithm uses one of the available entries. Otherwise, the algorithm searches for a “shared” entry. If at least one shared entry is available, then the algorithm uses one of the shared entries. Otherwise, the algorithm searches for a “dirty” entry. If at least one dirty entry is available, then the algorithm uses one of the dirty entries. In selecting a directory entry, the algorithm uses a “least-recently-used” (LRU) algorithm because an entry that was not recently used is more likely to be stale. Further, to improve system performance, the algorithm preferably uses a shared entry before using a dirty entry.

Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below

Abstract: A spin-valve magnetoresistive sensor includes a free layer of a ferromagnetic material, a pinned layer provided on the free layer and a pinning layer of an anti-ferromagnetic material provided on the pinned layer, the anti-ferromagnetic material being an ordered alloy containing manganese. The pinned layer includes a first pinned layer of a ferromagnetic material, a second pinned layer of a ferromagnetic material provided on the first pinned layer and an intermediate layer interposed between the first and second pinned layers such that the first and second pinned layers establish a super-exchange interaction in an anti-parallel manner. The second pinned layer has a magnetic moment smaller than a magnetic moment of the first pinned layer.

Abstract: The present invention provides a method and apparatus for providing a polysilicon type-1 ESD transistor in a flash memory chip. The method and apparatus include providing a select gate transistor that includes a gate, a floating gate, a medium doped junction, and a source and drain. The method and apparatus further include forming the source and drain by performing a lightly doped drain (LDD) mask and etch, performing a LDD spacer deposition and LDD spacer etch, and performing a N+ implant mask and a N+ implant.

Abstract: A new self clocking family of dynamic logic gates which replace footless or subsequent stage dynamic logic gates in multi-stage domino logic circuits. In a preferred embodiment, a multi-stage logic circuit is designed having a first stage which utilizes a traditional dynamic logic gate and a second stage which includes a new self-clocking dynamic logic gate. The output from the first stage is coupled to the input of the second stage such that the second stage is not dependent upon any type of clock signal for precharging. Instead, the second stage includes a dual transistor arrangement on the inter-stage inputs (i.e. the outputs from one stage which are input to subsequent stages) in order to precharge the output node at the second stage such that no type of clock signal is needed during precharge. Accordingly, the output from the second stage is efficiently precharged without using a delayed clock signal or any customized delay circuitry while minimizing through current by design.

Abstract: A capacitance pressure sensor that prevents leakage from outside the sensor to the reference pressure cavity, has a structure that can decrease defects due to leakage compared to conventional technology. An electrode comprising a thin metallic layer is formed on the upper surface of a glass substrate that forms one of the substrates of a pressure sensor and an external electrode is formed on the surface edge of the substrate. In addition, in the region where the silicon substrate is bonded, a feedthrough extending from the electrode to the external electrode is formed, and spine shaped layers with three braches for blocking leakage gas are formed perpendicularly to the feedthrough.