Abstract: A liquid crystal display device of the present invention has a structure in which vertically aligned liquid crystal is sealed between a TFT substrate and a CF substrate. Pixel electrodes in which slits are provided are formed on the TFT substrate, while cell gap holding spacers and domain defining projections are formed on the CF substrate. For example, positive type photoresist is coated on a common electrode. Then, first exposure is executed by using a mask for light-shielding spacer forming regions and projection forming regions, and then second exposure is executed by using a mask for light-shielding the spacer forming regions. Then, the photoresist is developed. Accordingly, the spacers and the projections, each having a different height, can be formed simultaneously.
Abstract: To realize a integrally constructed cooler of the heat pipe type which ensures the achievement of sufficient cooling capacity and the realization of a simple, compact and inexpensive cooler, that is especially low in height, employing and incorporating ingeniously a heat pipe, there is provided a heat pipe type cooler comprising: a heat receiving plate 3; a heat radiator having a configuration of a plurality of horizontally oriented heat radiation plates 5 extending vertically; and a heat pipe H having a generally U or V shaped profile, the middle portion of which is secured to the heat receiving plate 3: and wherein each end of the heat pipe H passes through the heat radiation plates 5.
Abstract: An alterable Common Flash Interface (“CFI”) is disclosed which includes a storage array which stores the CFI data. The storage array provides sub-circuits for encoding the CFI data. The sub-circuits comprise elements which can be altered by changing a single metal layer of the fabrication process.
Abstract: Disclosed herein is a magnetic tape unit having a magnetic head for reading and writing data from and onto a magnetic tape. The magnetic tape is traveled in contact with the magnetic head during a read/write operation of the magnetic head. During a rest period where the read/write operation of the magnetic head is not performed, a reciprocating motion of the magnetic tape by a small distance is performed with a predetermined period. A temperature in the vicinity of the magnetic head is detected by a temperature sensor. The predetermined period is changed according to the temperature detected by the temperature sensor. Accordingly, the adhesion of the magnetic tape to the magnetic head can be well prevented irrespective of the temperature inside the tape unit.
Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a top oxide layer using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800° C. by either an LPCVD or RTCVD deposition processor. The process further includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the top oxide layer using an HTO deposition process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.
Abstract: An apparatus for high speed signal propagation across a net in an integrated circuit operates with a driver that is coupled to the net, for driving signals across the net. A first transition assist driver (TAD) is coupled to a first node in the net and is capable of pulling the voltage level of the first node in response to the voltage level of the first node reaching a threshold value. The threshold value can be adjusted in order to increase the switching speed or, alternatively, the noise immunity of the first TAD. A second TAD is coupled to a second node in the net and is capable of pulling the voltage level of the second node in response to the voltage level of the second node reaching the threshold value. The apparatus is used for increasing the propagation speed of signals that are transmitted in a microprocessor block or other stages in an integrated circuit.
Abstract: A magneto-optical recording medium capable of perfectly masking a mark adjacent to a mark to be reproduced thereby improving a reproduction output. The magneto-optical recording medium includes a transparent substrate, a magnetic reproducing layer laminated on the transparent substrate, a nonmagnetic intermediate layer laminated on the magnetic reproducing layer, and a magnetic recording layer laminated on the nonmagnetic intermediate layer. The reproducing layer has an easy direction of magnetization in a plane at room temperature, and has an easy direction of magnetization perpendicular to a film surface at a given temperature or higher. The nonmagnetic intermediate layer is thin enough to allow magnetostatic bond between the recording layer and the reproducing layer at the given temperature or higher.
January 4, 1995
Date of Patent:
June 19, 2001
Ken Tamanoi, Keiji Shono, Sumio Kuroda, Motonobu Mihara, Koji Matsumoto
Abstract: A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the trench is formed such that the first trench having an aperture is formed slightly deeper than a drain diffusion layer on a semiconductor surface whereas the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral width of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.
Abstract: A tuning fork type vibrator including two arms and a base is supported by a supporting substrate mounted on a stem, and an oscillation limiting member formed from a ring-shaped rubber-like elastic body is mounted with its one face secured to the stem so as to surround the base. When an external vibration or impact is applied, the tuning fork type vibrator oscillates in response to the vibration or impact, but the oscillation range of the tuning fork type vibrator is limited by the presence of this oscillation limiting member, and thus bumping of the tuning fork type vibrator against the surrounding members such as the stem is prevented. Moreover, a gyro characteristic is not impaired, and a loss of the gyro function due to a stop of drive vibration does not occur.
Abstract: It is an object of the present invention to provide a cooling system capable of simultaneously cooling the electronic parts on a multichip module that is arranged so as to provide a predetermined function, wherein the cooling system can be easily and quickly attached to and detached from the module when necessary.
Abstract: An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.
Abstract: A cartridge transferring robot for use in a library apparatus which is capable of improving the accuracy of the cartridge inserting/extracting angle of a hand mechanism and further of ensuring the positional accuracy of the tip portion of the hand mechanism sufficient for direct insertion and extraction of a cartridge into/from a drive unit. In the present invention, for these purposes, a tilt mechanism for adjusting the angle of the cartridge inserting/extracting direction with respect to a horizontal plane is composed of a tilt base for supporting a picker section so that the picker section is swingable around a supporting shaft located on a picker section front surface side facing a place for insertion or extraction of the cartridge, and a swinging drive mechanism disposed on the rear side of the picker section for making the picker section swing around the supporting shaft with respect to the tilt base.
Abstract: Desired data recorded in a recording medium is read as a result of a head scanning a desired track, track tracking information for detecting the amount of displacement of said head with respect to the track and address information for identifying the recorded data are also recorded in said recording medium, and the track tracking information and the address information are used so that the head scans the desired track properly. The recording medium is used in which recording medium the track tracking information and the address information is disposed so that the head first scans the track tracking information and then scans the address information. Whether the track, which the head scans, is the desired track is determined from the address information. The amount of displacement of the head with respect to the track is detected from the track tracking information. The desired data is read from the desired track.
Abstract: A thin multi-layer circuit board having alternately stacked wiring pattern layers, including a top wiring pattern layer and insulating layers on an insulating plate-like substrate. The wiring pattern layers are electronically connected through vias in the insulating layers to form a predetermined circuit pattern by said wiring pattern layers. A metallic barrier layer is formed on the top wiring pattern layer, except at an exclusion zone of the metallic barrier layer. An electronic part-mounting pad layer and a remodeling pad layer are formed on the metallic barrier layer. The remodeling pad layer is arranged adjacent the electronic part-mounting pad layer, with the exclusion zone therebetween.
Abstract: This invention relates to a method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of said device, wherein at least some of the contaminate nitrogen has formed a bond with the surface of the silicon substrate in contact with the gate oxide layer in said gate region, said method comprising: contacting said gate oxide layer and contaminate nitrogen with a gas comprising ozone at a temperature of about 850° C. to about 950° C. for an effective period of time to break said bond; and removing said gate oxide layer and contaminate nitrogen from said surface of said silicon substrate.
Abstract: A magneto-optical information recording/reproducing apparatus in which a magneto-optical information recording medium at least including a first magnetic film having perpendicular magnetic anisotropy, and a second magnetic film to which information recorded on the first magnetic film is transferred by irradiation of a laser beam, is used so that a readout laser beam is irradiated onto the second magnetic film to thereby readout the information transferred to the second magnetic film. The apparatus includes a 2-split detection circuit for receiving the readout laser beam reflected from the second magnetic film of the recording medium, and a subtraction circuit in which output signals of the two detection elements of the 2-split detection circuit are subtracted from each other to generate a differential signal.
Abstract: An alterable Common Flash Interface ("CFI") is disclosed which includes a storage array which stores the CFI data. The storage array provides sub-circuits for encoding the CFI data. The sub-circuits comprise elements which can be altered by changing a single metal layer of the fabrication process.
Abstract: The present invention discloses a method for saving overhead programming time in a flash memory. In the preferred embodiment of the invention, a wordline voltage generation circuit and a bitline voltage generation circuit are electrically connected with a comparator circuit. During the programming operation, the comparator circuit compares a wordline programming voltage and a bitline enabling voltage generated by the voltage generation circuits to determine when the programming voltages reach a predetermined voltage level. Once the predetermined voltage level is reached, the comparator circuit sends an output signal to a state machine that initiates programming for at least one cell. The present invention provides advantages over prior methods of programming by reducing the time period that the state machine waits to initiate programming.
Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power source for generating a low power supply voltage on the order of 3 V or less. A wordline driver includes a booster for boosting the supply voltage to produce a wordline read voltage which is higher than the supply voltage, and applying the wordline voltage to a wordline. An upper clamp limits a maximum value of the wordline voltage to prevent read disturb. The upper clamp can be configured to reduce an amount by which the maximum value varies with the supply voltage, or to limit the maximum value to substantially a predetermined value.
October 5, 1998
Date of Patent:
October 17, 2000
Advanced Micro Devices, Fujitsu, Ltd.
Colin S. Bill, Jonathan S. Su, Takao Akaogi, Ravi P. Gutala
Abstract: In a parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements, each of the processor elements has a storage unit to store data to be processed, the controller controls operation of the processor elements, and the parallel computer system performs processing of the data based on a calculation control signal transmitted from the controller. The parallel computer system further a data collection unit connected between the processor elements and the controller for receiving output data from the processor elements, performing a predetermined calculation, and outputting calculated data to the controller; and a calculation control unit connected between the data collection unit and the controller for transmitting the calculation control signal from the controller to the data calculation unit to make it possible to perform the predetermined calculation in the data collection circuit.