Patents Assigned to FUJITSU SEMICONDUCTOR
  • Method for fabricating a transistor device with a tuned dopant profile
    Patent number: 9577041
    Abstract: A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 21, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Teymur Bakhishev, Sameer Pradhan, Thomas Hoffmann, Sachin R. Sonkusale
  • SEMICONDUCTOR DEVICE HAVING INSULATING LAYERS CONTAINING OXYGEN AND A BARRIER LAYER CONTAINING MANGANESE
    Publication number: 20170047246
    Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.
    Type: Application
    Filed: October 27, 2016
    Publication date: February 16, 2017
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hirosato OCHIMIZU, Atsuhiro TSUKUNE, Hiroshi KUDO
  • Semiconductor device and method for manufacturing the same
    Patent number: 9559058
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 31, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
  • Integrated circuit device body bias circuits and methods
    Patent number: 9548086
    Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 17, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, David A. Kidd, Augustine Kuo
  • Semiconductor device, semiconductor integrated circuit device, and electronic device
    Patent number: 9543228
    Abstract: A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: January 10, 2017
    Assignees: FUJITSU LIMITED, FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kouichi Kanda, Nobumasa Hasegawa
  • Semiconductor device having multiple wells for low- and high-voltage CMOS transistors
    Patent number: 9524899
    Abstract: There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a first well and a second well of the first conductivity type; introducing a second impurity of a second conductivity type, to thereby form a third well of the second conductivity type and introducing the second impurity into a region between the first well and the second well, to thereby form a separation well of the second conductivity type; and further introducing a third impurity of the second conductivity type into the region between the first well and the second well.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: December 20, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yasunobu Torii
  • Reducing or eliminating pre-amorphization in transistor manufacture
    Patent number: 9514940
    Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: December 6, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lance S. Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
  • Semiconductor wafer and method for manufacturing semiconductor device
    Patent number: 9508559
    Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: November 29, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, Mitsufumi Naoe, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya Sashida
  • Advanced transistors with punch through suppression
    Patent number: 9508800
    Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 29, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
  • CMOS gate stack structures and processes
    Patent number: 9508728
    Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: November 29, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Pushkar Ranade, Scott E. Thompson
  • Low power semiconductor transistor structure and method of fabrication thereof
    Patent number: 9496261
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: November 15, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachrin R. Sonkusale, Weimin Zhang
  • Buried channel deeply depleted channel transistor
    Patent number: 9478571
    Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 25, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
  • Semiconductor device and method of manufacturing the same
    Patent number: 9472611
    Abstract: A semiconductor device includes: a semiconductor substrate; a base above the semiconductor substrate; a first conductive plug in the base; a memory cell region in the base; and a logic circuit region connected to the memory cell region, the logic circuit including a first capacitor. The first capacitor includes: a first bottom electrode, a part of a lower surface of the first bottom electrode being in contact with the first conductive plug; a first insulating film on the first bottom electrode; and a first top electrode on the first insulating film. The first top electrode is spaced apart from the first conductive plug in planar view.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: October 18, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hitoshi Saito, Wensheng Wang
  • Semiconductor device and method for fabricating semiconductor device
    Patent number: 9470940
    Abstract: A semiconductor device includes a first electrode layer and a second electrode layer disposed over a substrate, a first insulating layer disposed over the first electrode layer, and a reflective electrode layer disposed on the first insulating layer and electrically connected to the first electrode layer, wherein the second electrode layer is exposed externally, and a thickness of the second electrode layer is greater than a thickness of the reflective electrode layer.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: October 18, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tomiyasu Saito, Tatsuya Mise, Yoshio Matsuzawa, Tetsuya Takeuchi
  • Electronic apparatus having non-volatile memory and method for controlling the same
    Patent number: 9471483
    Abstract: Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said sector comprising a plurality of said portions, and the memory having at least three said sectors each of which is adapted to be erased independently of the others; and control means operable to control erasing of the sectors, wherein: the control means is configured to store in a plurality of the sectors other than a target said sector erasure information concerning an erasure procedure, the erasure procedure involving erasing the target sector, so that such information in the sectors may be inspected to establish a suitable recovery procedure following an interruption event.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 18, 2016
    Assignee: FUJITSU SEMICONDUCTOR EUROPE GMBH
    Inventors: Richard Landenbach, Marc Willam, Hartmut Sturm, Kai Dieffenbach
  • Semiconductor device and method of designing the same
    Patent number: 9455258
    Abstract: A semiconductor device includes: a semiconductor substrate having a memory cell array region and a peripheral circuit region; a ferroelectric capacitor formed over the semiconductor substrate in the memory cell array region; and a dummy capacitor formed over the semiconductor substrate in the peripheral circuit region, with a layered structure same as that of the ferroelectric capacitor, with an area larger than that of the ferroelectric capacitor, and with a line width not larger than the width of the ferroelectric capacitor.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: September 27, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kenji Watanabe
  • Semiconductor device
    Patent number: 9450058
    Abstract: A method for manufacturing a semiconductor device includes, forming, on a substrate, an element isolation insulating film which includes a protruding portion protruding above a level of a surface of the substrate, forming a first film on the substrate and on the element isolation insulating film, polishing the first film to expose the protruding portion, forming a first resist pattern which straddles the first film and the protruding portion after polishing the first film, patterning the first film using the first resist pattern as a mask to form a first pattern, and forming a sidewall film at side surfaces of the first pattern.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 20, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yusuke Morisaki
  • Transistor array structure
    Patent number: 9449967
    Abstract: A semiconductor circuit can include a plurality of arrays of transistors having differing characteristics and operating at low voltages and currents. A drain line drive signal may provide a potential to a drain line to which a selected transistor is connected. A row of drain mux circuits can provide reduced leakage current on the drain line drive signal so that more accurate current measurements may be made. A gate line drive signal may provide a potential to a gate line to which the selected transistor is connected. A column of gate line mux circuits can provide a gate line low drive signal to unselected transistors to reduce leakage current in unselected transistors so that more accurate drain current measurements may be made to the selected transistor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 20, 2016
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Richard S. Roy, Samuel Leshner
  • Scheduling in a multicore architecture
    Patent number: 9442886
    Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: September 13, 2016
    Assignees: Synopsys, Inc., Fujitsu Semiconductor Limited
    Inventor: Mark David Lippett
  • Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device
    Patent number: 9437737
    Abstract: A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 6, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hidenobu Fukutome, Tomohiro Kubo