Patents Assigned to FUJITSU SEMICONDUCTOR
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Patent number: 9853019Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.Type: GrantFiled: October 28, 2016Date of Patent: December 26, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Lawrence T. Clark, David A. Kidd, Augustine Kuo
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Publication number: 20170365528Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.Type: ApplicationFiled: August 31, 2017Publication date: December 21, 2017Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hidenobu Fukutome, Hiroyuki Ohta, Mitsugu Tajima
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Patent number: 9838012Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.Type: GrantFiled: April 6, 2017Date of Patent: December 5, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Scott E. Thompson, Lawrence T. Clark
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Patent number: 9830241Abstract: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.Type: GrantFiled: August 10, 2015Date of Patent: November 28, 2017Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventors: Mark David Lippett, Ayewin Oung
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Patent number: 9825171Abstract: A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.Type: GrantFiled: August 9, 2016Date of Patent: November 21, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hidenobu Fukutome, Tomohiro Kubo
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Patent number: 9818701Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.Type: GrantFiled: April 1, 2016Date of Patent: November 14, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazutaka Yoshizawa, Taiji Ema, Takuya Moriki
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Patent number: 9812550Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: January 30, 2017Date of Patent: November 7, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 9812497Abstract: A lower conductive film is formed over a substrate. A first insulating film is formed in the lower conductive film. An opening which reaches the lower conductive film is formed in the first insulating film. An MTJ multilayer film having a magnetization free layer, a tunnel barrier layer and a magnetization fixed layer is deposited over the lower conductive film in the opening and over the first insulating film. An upper electrode is formed over the MTJ multilayer film. By removing the portion of the MTJ multilayer film deposited over the first insulating film, an MTJ device composed of the portion of the MTJ multilayer film which has remained in the opening is formed. A lower electrode composed of the lower conductive film is formed under the MTJ device by removing at least a part of the first insulating film, and a part of the lower conductive film.Type: GrantFiled: March 24, 2011Date of Patent: November 7, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Akiyoshi Hatada
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Patent number: 9812894Abstract: A power switching circuit includes a current mirror circuit to generate mirror currents, by transferring, at different mirror ratios, monitored currents that are obtained by monitoring power supply voltages, a selector to select the mirror currents with a combination having the different mirror ratios for the monitored currents, according to a switching state of the power supply voltages, a comparator to compare the mirror currents selected by the selector and output a comparison result, and a switching circuit to switch a supply voltage to be supplied to a load to one of the power supply voltages, based on the comparison result.Type: GrantFiled: March 16, 2015Date of Patent: November 7, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Satoshi Yamada
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Publication number: 20170309561Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: ApplicationFiled: July 12, 2017Publication date: October 26, 2017Applicant: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Patent number: 9793172Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.Type: GrantFiled: October 20, 2016Date of Patent: October 17, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Lance Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
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Publication number: 20170293583Abstract: A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. The semiconductor integrated circuit fixes the logic level of the test signal line adjacent to the bus signal line in the system mode that uses the bus signal line. The semiconductor integrated circuit fixes the logic level of the bus signal line adjacent to the test signal line in the scan mode that uses the test signal line.Type: ApplicationFiled: March 3, 2017Publication date: October 12, 2017Applicant: MIE FUJITSU SEMICONDUCTOR LIMITEDInventor: Seiji Goto
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Patent number: 9786565Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.Type: GrantFiled: September 25, 2009Date of Patent: October 10, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hidenobu Fukutome, Mitsugu Tajima
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Patent number: 9786703Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.Type: GrantFiled: October 4, 2016Date of Patent: October 10, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
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Publication number: 20170287920Abstract: A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.Type: ApplicationFiled: June 15, 2017Publication date: October 5, 2017Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Wensheng Wang
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Patent number: 9779042Abstract: A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.Type: GrantFiled: August 12, 2013Date of Patent: October 3, 2017Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventor: Mark David Lippett
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Patent number: 9773794Abstract: An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.Type: GrantFiled: May 24, 2016Date of Patent: September 26, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Naoya Sashida
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Patent number: 9773733Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: GrantFiled: March 10, 2016Date of Patent: September 26, 2017Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Publication number: 20170263606Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.Type: ApplicationFiled: May 25, 2017Publication date: September 14, 2017Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
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Publication number: 20170250177Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Applicant: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Katsuyoshi Matsuura, Junichi Ariyoshi
