Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.

Abstract: A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening.

Abstract: A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a high side level shifter; a high side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the high side transistor; and a high side drive part, to which an output of the high side level shifter is supplied, and each of the low side drive circuits includes: a low side level shifter; a low side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the low side transistor; and a low side drive part, to which an output of the low side level shifter is supplied.

Abstract: A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region.

Abstract: A device can include an operational amplifier (op amp) circuit having a differential transistor pair, a first transistor of the differential transistor pair being formed in a first well of a substrate and a second transistor of the differential transistor pair being formed in a second well of the substrate; a body bias generator configured to generate at least a first body bias voltage for the first well, and not the second well, that varies in response to a first body bias control value; and a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.

Abstract: An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Abstract: After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.

Abstract: A memory test method is disclosed that can include providing at least one first switch of at least one test element coupled to a first memory section between a first node within a tested section and an intermediate node, coupling a test switch of the test element between the intermediate node and a forced voltage node, and coupling a second switch of the test element between the intermediate node and a second node; wherein the forced voltage node receives a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Abstract: A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.

Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.

Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.

Abstract: The disclosure relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.

Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.

Abstract: An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.

Abstract: A method can include selecting integrated circuit (IC) device fabrication process source variations; generating relationships between each process source variance and a device metric variance; and calculating at least one IC device metric value from the process source variations and corresponding relationships between each process source variance and a device metric variance.

Abstract: A power on reset circuit including: a startup circuit keeping an operation signal in an operating state during a power supply rises; a bias circuit keeping the operation signal in the operating state; a BGR circuit being activated during the operating state, and outputting a fixed voltage after a predetermined time elapses; a power supply divided voltage generation circuit outputting a reference voltage; an activation detection circuit generating a control signal which becomes inactive when a power supply rises and becomes active when the fixed voltage reaches a predetermined level; a comparator circuit outputting a power on signal and detecting as the power on signal when the reference voltage is greater than the fixed voltage; and a switch turning on and fixing an output of the comparator circuit to an inactive logical value while the control signal is inactive, and turning off while the control signal is active.

Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Abstract: A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included.

Abstract: A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.