Patents Assigned to Fujitsu
  • Patent number: 6464743
    Abstract: A mobile telecommunication station which is connected to a mobile telecommunication network and is provided with a mobile telecommunication service from the network, providing a function enabling unit (for example a voice coding unit) with a function which is masked in advance and is enabled by release of the mask and a masking control unit for watching predetermined air interface information (for example a broadcast information) from the mobile telecommunication network and releasing the mask of the function enabling unit according to an instruction, in extended information elements thereof, for releasing the mask. A half rate mobile telecommunication unit capable of increasing for example a channel capacity can therefore be released on the market early without waiting for the completion of the entire system on the network side. When the network side system is completed, the potential half rate functions of the mobile telecommunication unit are revealed all at once.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: October 15, 2002
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kanno, Yuuichi Abe, Hiroshi Ito, Tatsuo Hayashi
  • Patent number: 6467064
    Abstract: A Viterbi decoder for decoding a receive signal series encoded by an error correcting code is disclosed. The Viterbi decoder comprises a storage unit for storing a plurality of branch metrics, and a control unit for performing, upon receipt of the receive signal series, the processing of selecting a surviving path for each status using the branch metrics stored in the storage unit. The memory is prepared in accordance with the pattern of the receive signal series for storing a plurality of tables holding the branch metrics corresponding to each status. Each table holds the branch metrics in such a manner that the branch metrics of the two branches entering each status may be read by the control unit in the order of the branches constituting a trellis.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: October 15, 2002
    Assignee: Fujitsu Limited
    Inventors: Taizo Anan, Akira Nakagawa, Eishi Morimatsu
  • Patent number: 6466103
    Abstract: This invention is a duplexer device comprising two surface acoustic wave filters having band center frequencies different from each other and a line pattern for matching phases of the two surface acoustic Wave filters, wherein provided are: a wire bonding pad layer having a plurality of pads including. pads. for connecting the line pattern with terminals on the surface acoustic wave filters and pads for connecting a common terminal connected to. an external antenna with the line pattern; and a first pad connecting one of the surface acoustic wave filters and a first end of the line pattern and a second pad connecting the common terminal and a second end of the line pattern being arranged at positions that are the most distant from each other inside the wire bonding pad layer.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: October 15, 2002
    Assignees: Fujitsu Limited, Fujitsu Media Devices Limited
    Inventors: Yasuhide Iwamoto, Osamu Ikata, Nobuo Hirasawa, Hidenori Fukushima
  • Patent number: 6466694
    Abstract: A processing device performs region identification of an input image, and then performs an intra-region recognition process. The type code of each region and the individual code of a recognition result are then displayed, so that a user can modify both of the results of the region identification and the recognition process at one time. Furthermore, the processing device displays an original image close to the recognition result. If no correct answer exists among recognition candidates, code is added to the original image, and the original image with the code added is handled as a recognition result.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: October 15, 2002
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kamada, Katsuhito Fujimoto, Koji Kurokawa
  • Patent number: 6465892
    Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: October 15, 2002
    Assignees: Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Sharp Kabushiki Kaisha, Hitachi, Ltd., Fujitsu Limited, Matsushita Electronics Corporation, Mitsubishi Denki Kabushiki Kaisha, Rohm Co., Ltd.
    Inventor: Tadatomo Suga
  • Patent number: 6466545
    Abstract: An RM cell extractor extracts an RM cell, and outputs the RM cell to the CPU. The CPU computes a transmission-rate control parameter (for example, ICR) using the PCR, etc. set in the RM cell, and outputs the result to an RM cell inserter. The RM cell, inserter compares the transmission-rate control parameter sen in the RM cell with the transmission-rate control parameter input from the CPU, and rewrites the transmission-rate control parameter in the RM cell when it is larger than the transmission-rate control parameter input from the CPU.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: October 15, 2002
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Watanabe
  • Patent number: 6466554
    Abstract: A satellite data distribution method and system in which a subscriber can receive a data distribution service via a mobile communication system. The satellite data distribution system includes a mobile communication system having at least one base station unit communicating with the subscribers. The data to be distributed is transmitted from a center station of the satellite data distribution system to a satellite. The data is distributed from the satellite to the base station unit of the mobile communication system. Then, the data is distributed from the base station unit to the subscribers via the mobile communication system. Thus, a satellite data reception unit is not necessarily provided to each of the subscribers.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: October 15, 2002
    Assignee: Fujitsu Limited
    Inventor: Yasushi Okada
  • Patent number: 6466108
    Abstract: A surface acoustic wave resonator includes a piezoelectric substrate having formed thereon a interdigital transducer part comprising plural electrode fingers having a period pi that is substantially equal to a wavelength of a surface acoustic wave to be excited, and at least one reflector arranged in the vicinity of the interdigital transducer part to reflect the surface acoustic wave excited by the interdigital transducer part in a direction parallel to a propagation direction of the surface acoustic wave. The interdigital transducer part has three or more electrode fingers within the period pi, and the reflector has plural gratings having a period pr that is equal to a half of a wavelength of a surface acoustic wave propagating in the reflector.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: October 15, 2002
    Assignees: Fujitsu, Limited, Fujitsu Media Devices Limited
    Inventors: Takashi Matsuda, Jun Tsutsumi, Shogo Inoue, Osamu Ikata
  • Patent number: 6466760
    Abstract: A development device includes: a development roller a surface of which is made of electrically resistant material; a blade that comes in contact with the development roller so as to form a layer of developing agents, and has a predetermined thickness on the development roller, and possesses electrical conductivity; a bias power supply that applies a bias to the development roller and the blade; and a resistance provided between the blade and the development bias supply to establish electric connection therebetween. The resistance may be incorporated in the blade itself.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: October 15, 2002
    Assignee: Fujitsu Limited
    Inventor: Tsuneo Mizuno
  • Patent number: 6466080
    Abstract: A constant-current driver circuit for on-off controlling an output current at a high speed is provided. The constant-current driver circuit includes a first MOS transistor to which a reference current is provided and a second MOS transistor connected to the first MOS transistor for generating an output current having a predetermined ratio to the reference current. A switch circuit is connected to the second MOS transistor to on-off control the output current in accordance with the input signal. A bias circuit is connected to the gate of the second MOS transistor to provide a bias voltage to the gate of the second MOS transistor so that variation in the gate voltage of the second MOS transistor is suppressed.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: October 15, 2002
    Assignee: Fujitsu Limited
    Inventors: Takumi Kawai, Akihiko Ono
  • Patent number: 6466542
    Abstract: In a usage parameter control device for an asynchronous transfer mode communications system, a time counter is divided into multiple phases to enable audits of each of the virtual connections being handled by the system to be performed on a staggered group-by-group basis rather than all at once, thereby avoiding excessive delays in cell processing.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: October 15, 2002
    Assignee: Fujitsu Network Communications, Inc.
    Inventors: Michael P. Bottiglieri, Michael J. Samori
  • Publication number: 20020144418
    Abstract: A sensor unit includes a support body having a concave surface, a spherical body formed of a magnetic material and placed on the concave surface of the support body so as to roll freely thereon, a permanent magnet producing a magnetic field affecting the magnetic spherical body, and a magnetic sensor detecting a change in the magnetic field caused by the movement of said magnetic spherical body. The magnetic spherical body and the permanent magnet are provided to oppose each other with a given distance therebetween in a vertical direction. The magnetic sensor is provided between the magnetic spherical body and the permanent magnet. An output is produced in accordance with the detection by the magnetic sensor.
    Type: Application
    Filed: March 21, 2002
    Publication date: October 10, 2002
    Applicant: NAGANO FUJITSU COMPONENT LIMITED
    Inventors: Michiko Endo, Katsuya Funakoshi, Takashi Arita, Masayuki Kato, Shinichiro Akieda
  • Publication number: 20020147716
    Abstract: By comprising a question sentence input unit for receiving a question sentence for retrieval, a retrieval execution unit for retrieving data from a database storing data to be retrieved and extracting data similar to the question sentence inputted by the question sentence input unit, a word contribution degree calculation unit for calculating the contribution degree of a word contributing to the extraction by the retrieval execution unit and a word contribution degree output unit for the contribution degree calculated by the word contribution degree calculation unit together with the corresponding word, the word to which importance is attached can be reported to a user.
    Type: Application
    Filed: October 9, 2001
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Isao Namba
  • Publication number: 20020145899
    Abstract: A content addressable memory device which determines the top priority entry data without assigning priorities to addresses. If ternary data stored in a cell is invalid data, and other cell at the same bit position stores valid data of entry data identical to an entry key, the entry data is determined not to be a candidate of the top priority entry data. The last entry data which has not determined not to be a candidate is determined to be the top priority data. Compared to the conventional technology which relied on the relationship between a memory address and a priority, the performance of memory system is significantly improved.
    Type: Application
    Filed: February 25, 2002
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Miki Yanagawa
  • Publication number: 20020145480
    Abstract: An oscillator circuit which generates an oscillator signal that ensures the generation of a stable internal supply voltage. The oscillator circuit has a periodic circuit which includes a switch circuit. A method of controlling the oscillator circuit includes the steps of operating the periodic circuit using the switch circuit in response to a first control signal when the first control signal is in a first state to generate a first oscillator signal having a first frequency, and operating the periodic circuit using the switch circuit in response to a second control signal when the first control signal is in a second state to generate a second oscillator signal having a period synchronized to a period of the second control signal having a second frequency.
    Type: Application
    Filed: February 19, 2002
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Syuichi Saito
  • Publication number: 20020145934
    Abstract: Data is stored into a plurality of first memory blocks, and regeneration data for regenerating this data is stored into a second memory block. In a read operation, either a first operation for reading the data directly from a first memory block selected or a second operation for regenerating the data from the data stored in unselected first memory blocks and the regeneration data stored in the second memory block is performed. This makes it possible to perform an additional read operation on a first memory block during the read operation of this first memory block. Therefore, requests for read operations from exterior can be received at intervals shorter than read cycles. That is, the semiconductor memory can be operated at higher speed, with an improvement in data read rate.
    Type: Application
    Filed: December 5, 2001
    Publication date: October 10, 2002
    Applicant: Fujitsu Limited
    Inventors: Toshiya Uchida, Yasurou Matsuzaki
  • Publication number: 20020146998
    Abstract: In a single-to-differential conversion circuit for converting a single signal into a differential signal formed of first and second signal components: a source-grounded (or emitter-grounded) first transistor receives the single signal at the drain (or collector); the gate (or base) and drain (or collector) of the first transistor are connected; the gate (or base) of a source-grounded (or emitter-grounded) second transistor is connected to the gate (or base) of the first transistor; the drain (or collector) of a gate-grounded (or base-grounded) third transistor outputs the first signal component; the source (or emitter) of the third transistor is connected to the drain (or collector) of the first transistor; the drain (or collector) of a gate-grounded (or base-grounded) fourth transistor outputs the second signal component; and the source (or emitter) of the fourth transistor is connected to the drain (or collector) of the second transistor.
    Type: Application
    Filed: February 28, 2002
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Wakako Hoshino, Noriaki Shirai
  • Publication number: 20020145819
    Abstract: A servo track writer for writing a servo track signal to a disk medium in a disk drive including the disk medium, a head for reading/writing information from/to the disk medium, and an internal actuator for moving the head across tracks formed on the disk medium. The internal actuator has a rotatable carriage for supporting the head. The servo track writer includes an external actuator having an arm, a solid deformation element provided in relation to the arm, and an effector mounted on the arm; an internal actuator control unit for controlling the internal actuator; an external actuator control unit for controlling the external actuator; a solid deformation element control unit for controlling the solid deformation element; and an arm position detecting device for detecting a position of the arm. The solid deformation element is divided into a first segment functioning as an actuator for minutely displacing the carriage, and a second segment functioning as a sensor for detecting a position of the effector.
    Type: Application
    Filed: August 30, 2001
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Seiji Kino, Hirofumi Ohsawa, Yukio Ozaki
  • Publication number: 20020145927
    Abstract: There is intended to provide a semiconductor integrated circuit device capable of lowering the power consumption during data-write operation, enhancing operation speed, and reducing noises for stable operation. In the semiconductor integrated circuit, an active signal ACT to be inputted to a sense amplifier signal circuit SC1 is latched by a command latch circuit and outputted to a terminal N11. The terminal N11 outputs a control signal EDC1 via a timing adjusting circuit. The control signal EDC1 works to output a sense amplifier activating signal LE via a timing adjusting circuit and output buffer circuit and at the same time, the control signal EDC1 is outputted to a column switch signal circuit CS1. From the Column switch signal circuit CS1, a pulse signal is outputted via input of a control signal ACL, a pulse output circuit, and a terminal N13. In a logical circuit, AND processing is conducted between the pulse signal and an inversion signal of the control signal EDC1.
    Type: Application
    Filed: September 7, 2001
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Kazumi Kojima, Yasushige Ogawa, Hiroyuki Sugamoto
  • Publication number: 20020145929
    Abstract: A control circuit for increasing the speed of a device responding to a control request from an external device when the external control request is overlapped with an internal control request. The control circuit includes a first signal processing unit for receiving the first control signal and generating a first processed signal. The first signal processing unit includes a filter for filtering the first control signal. A second signal processing unit receives the first control signal and generates a second processed signal. An arbiter receives the second processed signal and the second control signal, determines which one of the received signals is to be given priority, and generates a determination signal based on the determination. A main signal generator generates the main signal from the determination signal or the first processed signal based on the determination signal.
    Type: Application
    Filed: January 3, 2002
    Publication date: October 10, 2002
    Applicant: Fujitsu Limited
    Inventor: Shigemasa Ito