Patents Assigned to Fujitsu
  • Publication number: 20020145906
    Abstract: Nonvolatile semiconductor memory has a core-side cell array having word lines, bit lines and memory cells; a reference-side cell array having word lines, bit line, and reference cell; and, a sense amplifier which compares a core-side input voltage corresponding to a bit line current in the core-side cell array, and a reference-side input voltage corresponding to the bit-line current in the reference-side cell array. The core-side decoder-driver and reference-side decoder-driver drive the core-side and reference-side word lines to the power supply voltage at a first time at the end of the address change detection pulse, and, at a second time a prescribed time after the end of the address change detection pulse, drive the core-side and reference-side word lines to a boost voltage level higher than the power supply voltage. The sense amplifier begins comparison of the core-side and the reference-side input voltages after the second time.
    Type: Application
    Filed: March 22, 2002
    Publication date: October 10, 2002
    Applicant: Fujitsu Limited
    Inventors: Yuichi Einaga, Yasushi Kasa
  • Publication number: 20020145034
    Abstract: The present invention relates to a library apparatus for accommodating different types of recording medium, such as magnetic tapes, in combination. By a method for reading markers, in which the type of the recording medium and its volume label are recorded, by moving a reader, and a construction for sorting and accommodating the different types of recording medium, the markers can be read at a high speed.
    Type: Application
    Filed: May 23, 2002
    Publication date: October 10, 2002
    Applicant: Fujitsu Limited
    Inventors: Hiroshi Shimada, Noriaki Matsuzaki, Takahiro Asahara
  • Publication number: 20020145933
    Abstract: A semiconductor memory device that reduces the time for conducting a multiple word line selection test and operates stably. The semiconductor memory device includes memory cell blocks, row decoders, sense amps, block control circuits, and sense amp drive circuits. Each block control circuit generates a reset signal. The reset signal is used to select the word lines with the row decoders at timings that differ between the blocks. Each block control circuit provides the reset signal to the associated row decoder. The block control circuit also provides the reset signal to the associated sense amp drive circuit so that the sense amps are inactivated at timings that differ between the blocks.
    Type: Application
    Filed: November 28, 2001
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Yuji Nakagawa
  • Publication number: 20020145930
    Abstract: An external command receiving circuit receives an external command signal supplied from the exterior, in synchronization with one transition edge of a first clock signal. An internal command receiving circuit receives an internal command signal internally generated, in synchronization with the other transition edge of the first clock signal. Namely, receiving operation of the internal command signal by the internal command receiving circuit shifts from that of the external command signal by the external command receiving circuit by at least a half cycle of the first clock signal. Immediately after starting an operation according to the external command signal, a control circuit for operating an internal circuit does not receive an operation request according to the internal command signal. This can prevent conflict in operation between the internal circuit according to the external command signal and the internal circuit according to the internal command signal, and also prevent malfunction.
    Type: Application
    Filed: January 7, 2002
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Yoshihide Bando
  • Publication number: 20020145459
    Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.
    Type: Application
    Filed: May 31, 2002
    Publication date: October 10, 2002
    Applicant: Fujitsu Limited
    Inventor: Yoshinori Okajima
  • Publication number: 20020145625
    Abstract: A distributed processing system wherein client-side process is simplified and system reliability is improved. An information transmission requesting section makes a request for transmission of information, and an information providing section provides received information to a user. An information management section manages the information, and an information relaying/transmitting section relays the information to be transmitted to a client application. An account authentication section verifies authenticity of account of the client application, and an information storage section stores the information. After the authenticity is verified, a service application control section controls the start and termination at logon and logoff, respectively, of a service application corresponding to the client application.
    Type: Application
    Filed: May 22, 2002
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Hiroaki Komine, Noriyuki Yokoshi, Sachinobu Sakurada, Tsuyoshi Naka
  • Publication number: 20020145935
    Abstract: A timing signal generator receives a plurality of control signals in synchronization with a clock signal, and generates a timing signal according to a combination of the control signals. A delay circuit delays an input signal received asynchronously to the clock signal by a predetermined time. A receiving circuit receives the input signal which is delayed by the delay circuit, in synchronization not with the clock signal but with the timing signal. Namely, the receiving circuit operates asynchronously to the clock signal, and receives only necessary input signals for the semiconductor integrated circuit. This lowers operation frequency of the receiving circuit, thereby reducing power consumption. The number of the circuits to be operated in synchronization with the clock signal can be reduced, by which reduces standby current. An increase in the standby current is gradual even when frequency of the clock signal goes high.
    Type: Application
    Filed: January 22, 2002
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Yoshimasa Yagishita
  • Publication number: 20020146876
    Abstract: A semiconductor integrated circuit including a debugging support unit and a buffer memory for temporarily storing trace data, the debugging support unit comprising a break detection member that detects a break signal externally inputted and a break determining member that determines whether the break signal requests to shift to break processing after outputting all the trace data stored in the buffer memory or the break signal requests to shift to the break processing with immediately suspending trace data outputting.
    Type: Application
    Filed: March 21, 2002
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Toshiaki Saruwatari, Koutarou Tagawa
  • Publication number: 20020145413
    Abstract: A DC-DC converter includes N capacitors having identical capacitances, initially coupled in series, and supplied with an external power supply voltage to be charged thereby, and an circuit for coupling the N capacitors in parallel and varying a duty ratio of a charging timing, so as to vary an internal power supply voltage which is output from the DC-DC converter.
    Type: Application
    Filed: August 3, 2001
    Publication date: October 10, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Umeo Oshio
  • Publication number: 20020146217
    Abstract: An optical module including a substrate having a groove; an optical waveguide layer formed on the substrate, the optical waveguide layer including an optical waveguide core having first and second ends, the first end being aligned with the groove, and an optical waveguide cladding covering the optical waveguide core; a ferrule having a through hole; and an optical fiber inserted and fixed in the through hole. The ferrule has a flat cut portion for semicylindrically exposing a part of the optical fiber inserted and fixed in the through hole. The ferrule is fixed at the flat cut portion to the substrate so that the part of the optical fiber exposed to the flat cut portion is inserted into the groove of the substrate until one end of the optical fiber abuts against the first end of the optical waveguide core.
    Type: Application
    Filed: January 30, 2002
    Publication date: October 10, 2002
    Applicant: Fujitsu Limited
    Inventors: Hiroyuki Nobuhara, Goji Nakagawa, Kazuhiro Tanaka
  • Publication number: 20020147661
    Abstract: A method of delivering sample pictures containing information about how to purchase the original picture data. A computer system stores picture data received from mobile stations over a network. It then creates sample pictures from the stored picture data. Each sample picture contains ordering information that shows where to purchase the original version of the picture data. When a request is received from a terminal station on the network, the computer transmits such sample pictures to the requesting station.
    Type: Application
    Filed: September 26, 2001
    Publication date: October 10, 2002
    Applicant: Fujitsu Limited
    Inventors: Hiroshi Hatakama, Tetsuya Tsukahara, Takahisa Hatakeyama, Hiroyuki Yahagi, Kenji Ishii, Takashi Ueki, Satoshi Muramatsu
  • Publication number: 20020146631
    Abstract: This invention relates to image formation toner, 2-component developer, image formation method and method for manufacturing image formation toner, for preventing clogging of the filter. Toner is used in which the ratio of the component measured by GPC to have a molecular weight between 500 to 1000 is 10 parts by weight or less with respect to 100 parts by weight of the entire toner. Since the case of clogging of the HEPA filter is the 500 to 1000 molecular weight component, clogging of the filter is prevented by reducing this component.
    Type: Application
    Filed: February 28, 2002
    Publication date: October 10, 2002
    Applicant: Fujitsu Limited
    Inventors: Yasushige Nakamura, Yasuyuki Furuse, Seijirou Ishimaru
  • Patent number: 6462880
    Abstract: A bar code reader having two reading windows, i.e., a bottom window and a side window. An increased number of scanning lines are used for constituting scanning patterns for scanning bar codes, and the arrangement of the optical system is contrived to decrease the whole size of the bar code reader and, particularly, to decrease the depth of the bar code reader. A source of laser light, a splitter for splitting the laser beam emitted from the laser light source into two, a reflection mirror for transmitting one beam from the splitter to a polygon mirror, the polygon mirror which rotates to scan the incident laser beam, a mirror system for emitting the beam reflected by the polygon mirror through the reading window, and a focusing member for focusing the beam reflected by the bar code onto a detector that detects the beam reflected by the bar code, are arranged on the same line in the bar code reader. By using a concave mirror, furthermore, the beam reflected by the bar code is folded back to one detector.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventors: Masanori Ohkawa, Toshiyuki Ichikawa, Hiroshi Watanuki, Kozo Yamazaki
  • Patent number: 6461194
    Abstract: A connector for an electronic device has a plug with signal contacts and ground contacts arranged in an alternating sequence in two parallel rows. A shield portion is provided on each ground contact so as to cover an area around adjacent signal contacts so as to reduce crosstalk between adjacent signal contacts.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Takamisawa Component Ltd.
    Inventors: Satoshi Katoh, Tadashi Kumamoto, Takeshi Okuyama, Hideo Miyazawa, Yukihiro Maitani
  • Patent number: 6462424
    Abstract: A method of producing a semiconductor device includes a device body producing step, electrically coupling leads and a semiconductor chip, and producing a device body by encapsulating the semiconductor chip by a resin package so that portions of the leads are exposed from the resin package, a honing step, carrying out a honing process using a polishing solution at least with respect to a resin flash adhered on the portions of the leads exposed from the resin package, an etching step, removing an unwanted stacked layer structure formed on the leads by carrying out an etching process after the honing step, and a plating step, carrying out a plating process with respect to the leads after the etching step to form a plated layer made of a soft bonding material. The honing step removes a portion of the unwanted stacked layer structure in addition to the resin flash.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventors: Masaaki Seki, Katsuhiro Hayashida, Mitsutaka Sato, Toshio Hamano
  • Patent number: 6463260
    Abstract: A method of delivering data from a transmission station to receiver stations via satellite communication links includes the steps of delivering delivery data from the transmission station to the receiver stations via the satellite communication links, checking if the delivery data is successfully received at each of the receiver stations, sending results of the check from the receiver stations to the transmission station, generating control data from the results of the check at the transmission station, the control data indicating which receiver station failed to receive the delivery data and which receiver station succeeded in receiving the delivery data, sending the control data from the transmission station to the receiver stations, and transferring the delivery data in response to the control data from a first one of the receiver stations having succeeded in receiving the delivery data to a second one of the receiver stations having failed to receive the delivery data.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventor: Kazuyoshi Nagai
  • Patent number: 6462374
    Abstract: To provide a semiconductor device which can retain information for a long period of time even in a case that the tunnel insulation film is thin. A semiconductor device comprises a first insulation film 14 formed on a semiconductor substrate 10, a floating gate electrode 22 formed on the first insulation film, a second insulation 24 film formed on the floating gate electrode, and a control gate electrode 26 formed on the second insulation film. A depletion layer is formed in the floating gate electrode near the first insulation film in a state that no voltage is applied between the floating gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventors: Tatsuya Usuki, Naoto Horiguchi
  • Patent number: 6462993
    Abstract: An address input circuit outputs an address signal from exterior as an internal address signal. A latching circuit accepts the internal address signal, and supplies the accepted signal to an internal circuit in conformity to the operating timing of the internal circuit. A redundancy judgement circuit judges whether or not the internal address signal yet to be accepted into the latching circuit is of a defect address, and outputs the judgement result as a redundancy judgement signal. A redundancy latching circuit accepts the redundancy judgement signal, and supplies the accepted signal to the internal circuit in conformity to the operating timing of the internal circuit. The use of the address signal before it is latched for redundancy judgement allows the redundancy judgement to be performed at earlier timing. Therefore, the amount of time needed for the read operation and write operation can be reduced.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventor: Naoharu Shinozaki
  • Patent number: 6462844
    Abstract: In a wavelength-division multiplexing transmission technique, a loss difference compensator for compensating a loss difference of an optical signal at each wavelength generated in a wavelength-division-multiplexed optical signal due to a wavelength-dependent transmission loss characteristic of an optical transmission line is disposed to the optical transmission line for transmitting the wavelength-division-multiplexed optical signal having a wide wavelength band in which optical signals at a plurality of wavelengths are wavelength-division-multiplexed to compensate the loss difference of the optical signal at each wavelength generated in the wavelength-division-multiplexed optical signal due to the wavelength-dependent transmission loss characteristic of the optical transmission line and a dispersion compensator, thereby transmitting the wavelength-division-multiplexed optical signal in a wide wavelength band for a long distance.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventors: Yutaka Kai, Hiroshi Onaka
  • Patent number: 6461942
    Abstract: Semiconductor chips are formed on a wafer. The wafer is diced, while a dicing tape applied to the wafer is kept intact. Each of the semiconductor chips is fixed by suction and then removed from the dicing tape. Each of the semiconductor chips is unfixed by ceasing the suction and picked up and conveyed.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventors: Mitsuhisa Watanabe, Kazuo Teshirogi, Eiji Yoshida, Yuzo Shimobeppu, Yoshito Konno, Kyouhei Tamaki