Patents Assigned to Fujitsu
  • Publication number: 20020144125
    Abstract: A semiconductor integrated circuit includes one or more function blocks, a nonvolatile memory unit which stores therein coded license information, and a decoder circuit which decodes the license information stored in the nonvolatile memory unit, and makes one of the function blocks either usable or unusable depending on the decoded license information.
    Type: Application
    Filed: January 17, 2002
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi Watanabe, Noburu Rinoie, Takamitsu Kobayashi
  • Publication number: 20020140006
    Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.
    Type: Application
    Filed: March 6, 2002
    Publication date: October 3, 2002
    Applicant: Fujitsu Quantum Devices Limited
    Inventors: Yutaka Mimino, Osamu Baba, Yoshio Aoki, Muneharu Gotoh
  • Publication number: 20020142495
    Abstract: For a semiconductor device including a gate electrode in an area of part of a surface of a semiconductor substrate, a gate length is determined and to be set as an upper-limit gate length. For a semiconductor device of which a gate length is almost equal to the upper-limit gate length, an impurity implantation condition is determined to calculate a representative impurity concentration distribution. A limit gate length is obtained according to the representative impurity concentration distribution. For a semiconductor device of which a gate length is equal to or greater than the limit gate length and equal to or less than the upper-limit gate length, an impurity concentration distribution of the semiconductor device is calculated according to the representative impurity concentration distribution. Characteristics of the semiconductor device are obtained according to the impurity concentration distribution. This method reduces the period of time to calculate the characteristics of the semiconductor device.
    Type: Application
    Filed: August 29, 2001
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Akihiro Usujima
  • Publication number: 20020140652
    Abstract: Since the drive data for display or their correction values are stored in correspondence with the combination of the upper bits of the current frame image data and the upper bits of the previous frame image data, the capacity of the high-speed memory circuit that stores the conversion table can be reduced. Accompanying the reduction in the capacity of the conversion table, since the precision of the display drive data or their correction values becomes lower, an interpolation circuit is provided and, by means of an interpolation calculation the display, drive data or their correction values having increased precision is generated and consequently the input image data is corrected to generate the display drive data.
    Type: Application
    Filed: March 8, 2002
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Toshiaki Suzuki, Koshu Yonemura, Katsuyoshi Hiraki, Hiroshi Yamazaki, Katsunori Tanaka
  • Publication number: 20020140058
    Abstract: In a semiconductor chip, a second power source pad, to which a ground potential is applied, is arranged adjacent to a first power source pad, to which a power source potential is applied, signal pads are arranged adjacent to the second power source pad by the number corresponding to a size of an external part such as a bypass capacitor inserted between power source terminals in an IC chip, and further, a third power source pad, to which the ground potential is applied, is arranged adjacent to the signal pad. The second power source pad or the third power source pad is selected according to the size of the external part, and then, is connected to a lead terminal, to which the ground potential is applied, in an IC chip, thereby providing a power source terminal, to which the ground potential is applied.
    Type: Application
    Filed: December 14, 2001
    Publication date: October 3, 2002
    Applicant: Fujitsu Limited, Kawasaki, Japan
    Inventors: Yutaka Takinomi, Kazushi Sawai, Shinichi Watanabe
  • Publication number: 20020141263
    Abstract: A command storing control circuit stores in storing units a plurality of commands supplied the latest of the supplied commands so as to execute the memory operation. A command reading control circuit reads the commands stored in a command storing area during a test mode. If incorrect data are written into a semiconductor memory, causing the system mounting the semiconductor memory to become inoperable, the cause of the trouble can be efficiently determined by utilizing the commands stored in the command storing area. As a result, the efficiency of development of the system can be improved, for example, and the cost of developing the system can be reduced. Moreover, the quality of the system can be also improved.
    Type: Application
    Filed: December 17, 2001
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Shinsuke Kumakura
  • Publication number: 20020140468
    Abstract: The invention aims at securely generating an internal supply voltage when turning on the power supply of internal circuits in a semiconductor integrated circuit where the operation voltage is low, and securely resetting the internal circuits. The voltage generator generates an internal supply voltage supplied to the internal circuits based on the reference voltage by using the external supply voltage supplied from the exterior. That is, the voltage generator forcibly supplies the external supply voltage as internal supply voltage when the power-on reset signal is activated. Therefore, when the external supply voltage is low at the time of turning-on of the power, and the voltage generator does not operate normally, the internal supply voltage can be securely generated following the external supply voltage so as to be supplied to the internal circuits.
    Type: Application
    Filed: June 3, 2002
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiharu Kato, Nobuyoshi Wakasugi
  • Publication number: 20020141270
    Abstract: A semiconductor memory device which permits access even during refresh operation and also is low in power consumption. An address input circuit receives an input address, and a readout circuit reads out data from at least part of a subblock group arranged in a column or row direction and specified by the address input via the address input circuit. A refresh circuit refreshes at least part of a subblock group arranged in a row or column direction and intersecting with the subblock group from which data is read out by the readout circuit. A data restoration circuit restores data of a subblock where refresh operation and readout operation take place concurrently, with reference to data from the other subblocks and a parity block.
    Type: Application
    Filed: December 4, 2001
    Publication date: October 3, 2002
    Applicant: Fujitsu Limited
    Inventors: Yoshimasa Yagishita, Toshiya Uchida
  • Publication number: 20020144228
    Abstract: A thermal analysis in heating a print-circuit board in a reflowing furnace is simulated by a processor using data required for the design and thermal analysis of the printed-circuit board that carries solder-bonded components. The result of simulation indicates the possibility of existence of unmelted solder bonds heated at peak temperature below a predetermined lower limit and solder bonds heated at temperature above a predetermined upper limit. On the basis of the result, the components that are likely to be heated at inapplicable temperature are redesigned so that they can actually be heated at temperature in the predetermined range. The modification of design is displayed.
    Type: Application
    Filed: May 28, 2002
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Hiroki Uchida, Yasuo Yamagishi
  • Publication number: 20020141262
    Abstract: A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.
    Type: Application
    Filed: November 20, 2001
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Yoshimasa Yagishita, Toshiya Uchida
  • Publication number: 20020142240
    Abstract: It is a toner for optical fixing which contains a binder resin, a colorant, and an infrared light absorbent, and the infrared light absorbent has a coloring opacity of 20 or less, and of phthalocyanine compound and/or naphthalocyanine compound.
    Type: Application
    Filed: September 21, 2001
    Publication date: October 3, 2002
    Applicant: Fujitsu Limited
    Inventors: Yoshimichi Katagiri, Yasushige Nakamura, Shinichi Yaoi, Tomoaki Tanaka, Katsuji Ebisu, Makoto Fukuda, Hiroyuki Sasaki, Yojiro Kumagae
  • Publication number: 20020139857
    Abstract: A still image of a moving object is restored from portions including the object in an image by using a movement distance of the object during an exposure time and the difference value between output values of adjacent pixels, the movement distance being calculated as a number of pixels. Therefore, especially in cases where a moving bar code is imaged, even if the image of the bar code is blurred as a result of the movement of the bar code during imaging, a still image of the bar code in which the outlines of the black portions and white portions of the bar code are clear can be obtained. Accordingly, bar code information can be read out from the imaged bar code.
    Type: Application
    Filed: October 5, 2001
    Publication date: October 3, 2002
    Applicant: Fujitsu Limited
    Inventors: Mitsuharu Ishii, Toshitaka Aoki, Isao Iwaguchi, Hiroaki Kawai, Kozo Yamazaki, Mitsuo Watanabe
  • Publication number: 20020142274
    Abstract: A human resources mixture skill development method suitable for being used by an entity comprises: a human resources mixture skill definition step that defines achievement in skill items of a human resources mixture required by the entity; a human resources mixture skill measurement step that measures achievement in the skill items of the current human resources mixture of the entity; and a first training path calculation step that generates training paths including combinations of a plurality of training courses so as to fill in differences between the achievement in the skill items defined in the human resources mixture definition step and the achievement in the skill items measured in the human resources mixture skill measurement step, and derives a training path that has the best value of numeric data, each of the numeric data being preassigned to each of the training courses, from a plurality of the training paths generated.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 3, 2002
    Applicant: Fujitsu Limited
    Inventor: Akio Fujino
  • Publication number: 20020140007
    Abstract: A protective pattern is formed on a semiconductor substrate in a shape covering a circuit region and exposing an air bridge connecting portion, a metallic film and an insulating film are formed to cover the protective pattern, the metallic film and the insulating film are patterned to form air bridge wiring and an air bridge protective film covering the air bridge wiring, and thereafter, the protective pattern is removed to form a hollow between the air bridge wiring and the circuit region.
    Type: Application
    Filed: March 19, 2002
    Publication date: October 3, 2002
    Applicant: Fujitsu Quantum Devices Limited
    Inventor: Kazuyuki Sakamoto
  • Publication number: 20020139860
    Abstract: The present invention has an object of providing a recording medium control method, a data management apparatus, and a recording medium for managing data by duplicating the data in each of a plurality of recording media. Two IC cards are loaded into a data management apparatus. In duplicating data in the two loaded IC cards, the two IC cards store their card characteristic numbers for self-identification and the card characteristic number of each other's pair IC card. If the card characteristic number of the pair IC card stored in one IC card matches the card characteristic number of the other IC card, the two IC cards are controllable.
    Type: Application
    Filed: May 24, 2002
    Publication date: October 3, 2002
    Applicant: Fujitsu Limited
    Inventors: Akiko Ono, Hisayuki Nishimura
  • Publication number: 20020139474
    Abstract: A raw bar stripping off and cleaning jig has a stripping-off member on which transfer tools are placed, a base for supporting raw bars stripped off from the transfer tools, a stripping-off suction member for attracting the raw bars to separate the same from the transfer tools, and a cover member for supporting the raw bars, which are stripped off from the transfer tools and are placed on the base, from the top.
    Type: Application
    Filed: May 23, 2002
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Michinao Nomura, Tsutomu Honma
  • Publication number: 20020143672
    Abstract: A tele-inventory system for inventorying various kinds of commodities in a shop by an operator from a remote management apparatus installed remotely from the shop, includes, at shop, a camera for taking images of object commodities to be inventoried, a image-transmitter for transmitting the taken images of the object commodities to the remote management apparatus, and, at the remote management apparatus, an image-receiver for receiving the taken images of the object commodities from the image-transmitter and display for displaying the taken images of the object commodities, whereby the operator can make an inventory of the object commodities at the remote management apparatus with consulting the taken images of the object commodities which images have been displayed on the display. With this system, it is possible to inventory commodities sold and stocked in a department store or a convenience store from a remote place.
    Type: Application
    Filed: October 22, 2001
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Naoyuki Sawasaki
  • Publication number: 20020140088
    Abstract: A semiconductor integrated circuit has a 3-dimmensional interconnection line structure for high-speed operation. One aspect of the present invention, there is provided a monolithic microwave integrated circuit (MMIC) having a 3-dimmensional tournament tree shaped multilayer interconnection lines, wherein a single electric feeding point on a top surface of the MMIC is divided, layer by layer, into plural electrodes on the semiconductor substrate of the MMIC via a plurality of laminated interconnection layers and vertical interconnection layers therebetween shaped like a tournament tree.
    Type: Application
    Filed: March 1, 2002
    Publication date: October 3, 2002
    Applicant: Fujitsu Quantum Devices Limited
    Inventors: Yoshio Aoki, Yutaka Mimino, Osamu Baba, Muneharu Gotoh
  • Publication number: 20020143712
    Abstract: The present invention relates to a price information mediating process for providing selling price information of at least one product supplier to at least one user. The process includes the steps of: receiving product search conditions from the user; retrieving a normal selling price of a desired product from storage means in accordance with the product search condition from the user, the storage means including normal selling price information which have been pre-registered by the product supplier; sending the retrieved normal selling price to the user; receiving a desired purchasing price presented by the user; and sending the desired purchasing price to the product supplier.
    Type: Application
    Filed: August 31, 2001
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Jun Suzuki
  • Publication number: 20020141243
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array, a control circuit which repeatedly perform an automatic erasure operation with respect to an entirety of the memory cell array, the automatic erasure operation including a preparatory write operation prior to an erasure operation and a following erasure operation, and a counter which counts how many times the automatic erasure operation is performed with respect to the entirety of the memory cell array, wherein the control circuit stops the automatic erasure operation in response to an event that the counter counts a desired number.
    Type: Application
    Filed: August 24, 2001
    Publication date: October 3, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Takayuki Yoneda, Yasuhiko Tanuma