Abstract: The present invention relates to a head positioning method, its and a disk device for positioning the head to read a disk medium at a predetermined position, which demodulates accurate demodulation positions even when the head is moving. In a disk device comprising a disk medium (6), a head (4), an actuator (3) and a control circuit (19), the demodulation result is determined from the position signal of the head and speed is corrected by a correction value which depends on the moving speed of the head. Since the speed is corrected, accurate positions can be demodulated even when the head is moving.

Abstract: In the semiconductor integrated circuit, an auxiliary conductor is formed in a wiring layer beneath a signal wire which connects a position Vin estimated to generate static electricity and a position Vout to be protected from static electricity. The capacitance of a glass substrate can be reduced to 1/1000 of the capacitance of the interlayer insulating film. Accordingly, even if a voltage of 1000 to 2000 V is generated between a substrate conveying system and the auxiliary conductor, the glass substrate works as a dielectric, and the voltage generated between the auxiliary conductor and signal wire is only several volts.

Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

Abstract: Disclosed is a method of controlling direction of radio-wave emission of a base-station transmitter which emits radio waves upon providing the radio waves with directivity in the direction of a receiver. Two antennas of a base station that are disposed at different positions transmit first and second signals that have been spread by mutually orthogonal spreading codes. A mobile station has a phase detector for receiving the first and second signals transmitted from respective ones of the antennas and obtaining a phase difference between these signals, and a direction estimator for calculating the direction of the mobile station, as seen from the base station, based upon the phase difference and for feeding back a signal representing the calculated direction from the mobile station to the base station. The transmitter of the base station transmits data toward the receiver in the calculated direction using a directional antenna.

Abstract: A transmission unit which transports digital signals between different network systems, effectively converting the signals to resolve their differences in the specifications. A first signal interface transmits and receives first network signals. A second signal interface transmits and receives second network signals. A downward converter produces lower-level signals by converting received first and second network signals to a lower hierarchical level at which the first and second network systems are compatible with each other in terms of logical signal structure. An upward converter produces a higher-level signal by converting each given lower-level signal to an upper hierarchical level which complies with the first or second network system. A loopback unit provides loopback paths to route the lower-level signals from the downward converter to the upward converter, so that the first and second network signal will be converted in both directions.

Abstract: An xDSL transceiver comprising a transmission unit for transmitting a DMT-modulated signal through a subscriber line as a transmission path and a receiving unit for receiving the DMT-modulated signal from the subscriber line. The xDSL transceiver further comprises an echo signal suppression unit for suppressing the echo signal from the transmission unit to the receiving unit by matching the phase between the frame of the transmission signal and the frame of the receiving signal.

Abstract: The high frequency power amplifier comprises a detector which detects a collector output power (or base input power) of an amplifying transistor, and a DC/DC converter which changes a collector voltage of the amplifying transistor in proportion to the detected power. Thus, a DC power consumed by the amplifying transistor is controlled. A resistor for a base bias of the amplifying transistor is connected to the DC/DC converter, thereby interlocking the base bias control with the control of the DC/DC converter.

Abstract: The present invention is a method for manufacturing a non-volatile semiconductor memory cell of a structure provided with a trap gate between a word line serving as a control gate, and a channel region of a substrate, the trap gate is constructed of an insulating layer and capable of trapping a carrier. The trap gate constructed of the insulating layer can change a threshold of a transistor locally because the carriers injected and trapped inside do not move in the gate. As associated with it, the trap gate does not need to be separated between adjacent memory cells. In addition, the insulating layers for electrical isolation need to be formed on and under the trap gate constructed of the insulating layer. However, the gate insulating layer of the three-layers structure can be formed very thin and highly reliably compared with the conventional floating gate structure.

Abstract: The present invention relates to a liquid crystal display in multiple alignment or MVA mode in which liquid crystal molecules having negative dielectric anisotropy are aligned differently, and it is an object of the invention to provide a liquid crystal display having improved response characteristics while suppressing any reduction in transmittance.

Abstract: This invention relates to a non-contact developing method for applying a driving voltage, which is an AC voltage superimposed on a DC offset voltage, to a non-contact developing roller to develop toner, and which prevents the selective developing phenomenon from occurring. The velocity ratio between the flying velocity of toner with a large particle size and the flying velocity of toner with a small particle size changes according to the driving frequency f of the AC voltage (45) applied to the developing roller, so by setting the driving frequency f of the AC component within a range where selective developing of the toner does not occur, it is possible to effectively prevent the selective developing phenomenon from occurring.

Abstract: The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.

Abstract: An access violation of the program is monitored by the access monitor which is a hardware. The access monitor acquires a signal input from the CPU to a memory. The access monitor includes an access permission table as information of the memory region to be permitted to each program, and detects the access violation of the signal from the CPU by referring thereto. In this manner, the unjust access is monitored by the hardware, thereby preventing the unjust access by rewriting in software.

Abstract: The geometric texture and the graininess of an output image are improved in half tone processing using an error diffusion method. An image processing method where half tone processing is performed on input images using an error diffusion method comprising steps of generating a sine wave where the amplitude and the frequency are modulated according to the average value of the target pixel value and the peripheral pixel values, adding the diffused quantization errors, the target pixel value and the sine wave, quantizing the addition result by a predetermined number of grayscale levels, and calculating the quantization errors of the peripheral pixels from the errors by quantization. By applying a disturbance sine wave by the error diffusion method, diffusion errors can be uniformly dispersed, and geometric texture and graininess can be improved.

Abstract: In a data reproduction method and apparatus of the present invention, a Viterbi detection unit is provided, the Viterbi detection unit having a plurality of detectors each providing a first partial response signal with a first constraint length from a first sequence of samples derived from a first readout signal. One of connection and disconnection of the plurality of detectors in the Viterbi detection unit is selected in response to a timing signal, wherein, when the connection of the plurality of detectors is selected, the Viterbi detection unit provides a second partial response signal with a second constraint length from a second sequence of samples derived from a second readout signal, the second constraint length being different from the first constraint length.

Abstract: Data lines are wired next to each other. A sense amplifier receives the data and outputs an amplified signal. Dummy data lines are laid out along both sides of a data bus consisting of the data lines. The dummy data lines have the same voltage variation as the data lines during a read operation of the data stored in the memory cells. This reduces the potential differences between the data lines and the dummy data lines during a read operation. As a result, the outer data lines and the inner data lines become nearly equal to each other in coupling characteristics, and the lengths of time it takes for the data read to each of the data lines to rise become almost equal to each other. Since the data lines have smaller fluctuations in rising time, the read time (access time) is accelerated.

Abstract: A display device includes a display portion and a tilt mechanism. The tilt mechanism can be rotated around a rotation center and the display device can be installed on and removed from an external device such as a keyboard, bar code reader and a POS terminal. The display device may include a fixing member, used for fixing the display device to the external device, provided with the tilt mechanism.

Abstract: A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

Abstract: The invention provides a NAND type nonvolatile memory comprising: a sense circuit 100 having a constant current supply source P7 connected to a bit line to which memory cells are connected and a sense transistor N8 for sensing potential at the connection point thereof; a first reference potential ARVss on the opposite side from the bit line of the memory cells; and a second reference potential PBVss to which the source of the sense transistor is connected, wherein during Erase-verify operations the first reference potential ARVss and the second reference potential PBVss are controlled to predetermined positive potential.

Abstract: A plasma display device is comprised of a plasma display panel, a circuit board having a driving circuit for driving the plasma display panel, a main frame for supporting the circuit board, and a uniform heat-conducting plate to be fixed to the plasma display panel. In this structure, although the uniform heat-conducting plate is fixed to the plasma display panel by means of, for example, an adhesive, the main frame can be detached from the uniform heat-conducting plate when the plasma display panel is replaced. As a result, various complicated structures such as a radiating fin and a rib can be formed on the main frame because consideration of the possibility of discarding the main frame along with a PDP to be replaced is no longer necessary.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.