Abstract: There is provided a magnetic head which is able to enhance the magnetic field intensity to be generated by shaping a magnetic pole, and a method of manufacturing the same. The method of manufacturing a magnetic head, comprising the steps of forming a lower recording magnetic pole and an upper recording magnetic pole, and trimming partially an elongated pole in the vicinity of a floating surface of the upper recording magnetic pole and an upper portion of the lower recording magnetic pole positioned below and around the elongated pole by an ion milling method, wherein a core width of the elongated pole can be adjusted.

Abstract: The present invention relates to an optical cross connect unit comprising M wavelength separating sections for receiving multiplexed optical signals each having N kinds of wavelengths different from each other through M optical fibers, respectively, and for wavelength-separating each of the multiplexed optical signals into N optical signals, M optical reproduction relay sections each for conducting an optical reproduction and relay in a manner of making a conversion of each of the N optical signals, wavelength-separated in each of the wavelength separating sections, into an electric signal and then modulating it with a desired optical wavelength, a refill section for mutually refilling M sets of optical signals optically reproduced and relayed in the optical reproduction relay sections, a focusing section for focusing the M sets of optical signals refilled in the refill section, and a light source unit for supplying input lights having desired wavelengths to be modulated in the M optical reproduction relay se

Abstract: A transmission system comprises a plurality of transmission apparatuses which use a single channel commonly. Each transmission apparatus comprises switches for connecting and disconnecting transmission paths with adjacent transmission apparatuses, a line signaling-signal monitoring and detecting portion, and a network dividing logic portion which opens and closes the switches based on an output of the line signaling-signal monitoring and detecting portion. The network dividing logic portion closes switches of transmission paths between transmission apparatuses which perform a telephone conversation and opens the other switches.

Abstract: A semiconductor device has a normal mode and a test mode for testing the semiconductor device, and is provided with a first circuit which receives an input signal, a test signal and an output enable signal, and outputs the input signal in response to the output enable signal, a second circuit which is coupled to the first circuit and outputs the input signal obtained from the first circuit, and power supply pads which receive a power supply voltage which is supplied in common to the first circuit and the second circuit. The first circuit fixes an output impedance of the second circuit to a high-impedance regardless of the output enable signal when the test signal indicates the test mode.

Abstract: An internal voltage generation circuit with a small area, which has many correction points and can provide an output voltage with a high precision, has been disclosed. In this internal voltage generation circuit, some resistors, among the resistors which are connected in series constituting the feedback circuit, have different resistance and transfer gates are provided in parallel to the resistors of different resistance. This configuration has a decode function and, therefore, the decoder can be eliminated and the number of sets of an inverter, a transfer gate, and a resistor can also be reduced, resulting in a reduction in area without a reduction in the number of the correction points.

Abstract: It is an object of the present invention to provide a system to receive orders of merchandise such as merchandise sold in a supermarket from a large number of employees, for example, of a workplace, and to deliver the ordered merchandise in a bundle, thereby enhancing the employees' convenience and the efficiency of business.

Abstract: A system for controlling a bandwidth when receiving and reassembling a consecutive data stream transferred while segmented by AAL1 format cells which enables correct determination of non-P and P formats and reassembly of cells even when error arises in multiple bits including the CSI bit of an AAL1 cell or when adding dummy cells and thereby enabling prevention of a gap in data in a frame, comprising, in a data reassembly unit which reassembles received cells, an 8-cell buffer for storing 8 cells of a cycle of a sequence count (SC) of 0 to 7 and sending the cells out to a later stage after a check unit of a sequence number (SN) field confirms normalcy of the cells and a control unit for control so that the number of P format cells stored in the 8-cell buffer becomes 1 cell when 8 cells are stored in the 8-cell buffer.

Abstract: A semiconductor memory device having a self-refresh operation includes a detection circuit generating a detection signal when detecting a change of a given input signal, and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation.

Abstract: A semiconductor memory device having a self-refresh operation includes a first circuit generating a first signal that specifies a first self-refresh cycle by a non-volatile circuit element provided in the semiconductor memory device, a second circuit receiving a second signal that specifies a second self-refresh cycle via a terminal that is used in common to another signal, and a third circuit generating a pulse signal having one of the first and second self-refresh cycles, the pulse signal being related to the self-refresh operation.

Abstract: A semiconductor memory device of a dynamic type having an interface of a static-type semiconductor memory device includes a memory cell array, and a control circuit controlling a read operation to be initiated in response to a predetermined signal externally applied thereto before a read or write command is externally applied to the control circuit.

Abstract: A semiconductor memory device includes bit lines which transfer data of memory cells, a plurality of first sense amplifier circuits connected to odd-number lines of the bit lines, a plurality of second sense amplifier circuits connected to even-number lines of the bit lines, and a clamp-voltage generation circuit which supplies a first clamp voltage to the first sense amplifier circuits, and supplies a second clamp voltage to the second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.

Abstract: A semiconductor memory device is provided.

Abstract: An interactive data analysis support apparatus for supporting the analysis of data comprises: a cross tabulation display device for displaying according to specified summing up conditions a cross tabulation in which data to be analyzed is cross summed up, a cell specifying device for specifying at least one cell among a number of cells constituting the cross tabulation, and a graph display device for displaying the data to be analyzed as a graph within the range of the cell specified by the cell specifying device.

Abstract: A damping resistance 20 is connected between the drain D of an FET 10 and a first end T3 of an output transmission line 13, and a damping resistance 21 is connected between the drain D of an FET 11 and the first end T3. The source of the FET 10 and the gate of the FET 11 are connected to a ground plane on the back surface of a substrate through a via which has a parasitic inductance when a multiplied frequency exceeds 20 GHz. The gate of the FET 10 and the source of the FET 11 receive microwaves of the same frequency and phase through an input transmission line 12.

Abstract: A high-speed DRAM, which comprises a plurality of separated operation circuits that perform accessing the memory cell array according to the detection of the transition of input signals and prevents a fatal malfunction even when glitches are generated in input signals, has been disclosed. The DRAM is designed so that erroneous data is not written to or read from by varying the possibility (sensitivity) with which a plurality of separated operation circuits initiate the operation according to the ATD signal.

Abstract: Disclosed are a signal control apparatus, a transmission system and a signal resynchronization control method, which efficiently prevent the occurrence of slipping and execute high-quality signal resynchronization control. The signal control apparatus comprises a serial/parallel converting section, a window setting section and a parallel/serial converting section. The serial/parallel converting section performs serial/parallel conversion on an input signal to yield parallel data. The window setting section sets a small window having a readout guarantee area narrowed at an optimal position at the time of reading the parallel data when an operational state is unstable, and sets a large window having the readout guarantee area widened from the optimal position when the operational state is stable.

Abstract: A semiconductor storage device conducts a late-write operation. The semiconductor storage device comprises: a memory core circuit storing data; a data latch circuit storing preceding data corresponding to a preceding write-operation; an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and a control circuit. The control circuit controls a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.

Abstract: A reaction byproduct which is generated when a ferro-dielectric material film is etched is removed without giving adverse effect on the semiconductor element. After the etching of the ferro-dielectric material film, a wetting process may performed using an aqueous solution of phosphoric acid. After the ferro-dielectric material film is etched using the resist as the mask, the wetting process is also performed using the aqueous solution of phosphoric acid before and after the ashing of resist.

Abstract: A semiconductor device that optimally controls a current supply of internal power supply voltage generation circuits in accordance with the number of banks that are simultaneously activated. A control circuit adjusts the activated number of internal power supply voltage generation circuits in response to activation signals of the banks.

Abstract: Memory cell blocks respectively have a plurality of memory cell rows and a redundancy memory cell row for relieving a defect in these memory cell rows, memory cells being arranged in the memory cell rows. A first decoder selects any of the memory cell blocks. A second decoder selects any of the memory cell rows in the memory cell block. The operation of the second decoder not in use for decoding in the redundancy memory cell row is suspended when the redundancy memory cell row operates. The absence of unnecessary circuit operation allows a reduction in power consumption when the redundancy memory cell row operates. Even in a semiconductor integrated circuit having a plurality of memory banks each including the plurality of memory cell blocks, the first decoder, and the second decoder, it is possible to reduce power consumption when the redundancy memory cell rows operates.