Abstract: A semiconductor device including a plurality of chip units each defined by a side wall and arranged in a state such that a side wall of a chip unit abuts a corresponding side wall of an adjacent chip unit, and an interconnection structure for interconnecting a plurality of terminals of a side wall of a chip unit to corresponding terminals of a side wall of an adjacent chip unit that abuts the chip unit at the respective side walls.

Abstract: A circuit for enabling a chip, usable for both a first device capable of having m chips and a second device having more than m chips, includes a first generation unit which generates a chip-enable signal that includes a bit pattern of m bits for enabling one of the m chips indicated by a chip number, a second generation unit which generates a chip-enable generation signal that is to be decoded into a chip-enable signal of at least 2m bits for enabling one of the more than m chips indicated by the chip number, the chip-enable generation signal including a bit pattern identical to the bit pattern of m bits when the chip number is equal to a specific number, and a selection unit which selects and outputs the chip-enable signal generated by the first generation unit when the circuit is used for the first device, and selects and outputs the chip-enable generation signal generated by the second generation unit when the circuit is used for the second device.

Abstract: A semiconductor device and a method of producing the semiconductor device are provided. This semiconductor device includes a semiconductor chip, a printed wiring board, a heat spreader, a sealing resin, and solder balls. The printed wiring board is provided with the solder balls on an outer portion and a wiring layer on an inner portion. Wires are bonded to the wiring layer, and an opening is formed in the center of the printed wiring board. The heat spreader is bonded to the printed wiring board, with the semiconductor chip being thermally connected to the stage portion of the heat spreader. The sealing resin is made up of a first sealing resin portion and a second sealing resin portion. The first and second sealing resin portions sandwich the heat spreader.

Abstract: Disclosed is a Faraday rotator capable of reducing the temperature dependence on a Faraday rotation angle, thereby enhancing the temperature characteristic, particularly, in a service environment in which the magnetization direction is variable, and an optical device using the Faraday rotator. The Faraday rotator includes a Faraday element which rotates the polarization plane of polarized light rays passing through the Faraday element when an external magnetic field is applied to the Faraday element.

Abstract: A PDP not posing the problem that previous display data appears at the time of activation, and a wave generating circuit capable of generating a complex wave without the necessity of expanding a quantity of ROM data and of increasing a reading speed have been disclosed. A plasma display panel display comprising a plasma display panel that includes a plurality of cells to be selectively discharged to glow, a reset unit for bringing the plurality of cells to a given state, an addressing unit for setting the plurality of cells to states associated with display data, and a sustaining discharge unit for enabling the plurality of cells to glow according to the set states further comprises an operation halt factor detector for detecting the fact that a factor of halting the operation of the plasma display panel has occurred, and an initialization unit that when it is detected that the operation halt factor has occurred, initializes memory information in the plasma display panel.

Abstract: There is provided an online program-updating system which is capable of updating contents of a program without interrupting any services provided by the system. A management information storage section stores management information including operative status flags each indicative of the operative status of a corresponding program module and information of a version number associated with the corresponding program module. A program execution section updates operative status flags based on the operative statuses of the program modules. A version number check section makes a comparison between the version number of each program module of a revised program and that of each program module of the existing program in response to a download request, and determines that an update of the program is required, if the version number of the program module of the revised program is newer.

Abstract: A semiconductor memory device has a first ferroelectric memory cell in which data is written after the device is mounted on a board, and a second ferroelectric memory cell whose capacitance is larger than that of the first ferroelectric memory cell. This second ferroelectric memory cell is utilized as a memory cell in which cipher or the like are written in the fabrication process. The second ferroelectric memory cell is formed with a combination of a plurality of the first ferroelectric memory cells. In order to realize the second ferroelectric memory cell, word lines or plate lines corresponding to a plurality memory-cell rows may be short-circuited. Alternatively, bit lines corresponding to a plurality memory-cell columns may be short-circuited.

Abstract: A nonvolatile memory that has a plurality of floating gate type cell transistors comprises a read buffer circuit, connected to the bit line, that detects the threshold voltage states in the cell transistor. Each cell transistor can hold 2N threshold voltage states and accordingly, the read buffer circuit reads N bits of data. For this purpose, the read buffer circuit has a latch circuit that latches the read data in accordance with the detected threshold voltage state. This latch circuit has a first and second latch reversal circuit for reversing the latched state to the first or second state. When the read buffer circuit reads the first bit being held in the cell transistor, the latch circuit in its initial state is reversed or not reversed by the first latch reversal circuit in accordance with the detected first and second threshold voltage state, or third and fourth threshold voltage state, and that latch state is output as the first data.

Abstract: A data information management system for 2D/3D model data which unwarily manages design information in the form of bulk data. The system allows for real time information transmission of device/component data and eases data cooperation between the design side and the manufacturing side. The unitary management of the management information of model data is performed by a common metaserver. A plurality of bulk servers respectively maintain, for example according to category, the individual model data which has been designed. Workstations, which access design information, acquire management information of model data from the metaserver. Based on the management information, the workstations access the appropriate bulk server which maintains the required model data. During implementing/updating of the model data, management information is registered by the metaserver, and model data is stored in the bulk servers. The metaserver, bulk servers, and workstations perform communication via a WAN or LAN network.

Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.

Abstract: The first input route information with a virtual path identifier, a virtual channel identifier and a line identifier set in the header of an input cell is compressed, and a base address with a lower number of bits than the input route information is generated from a part of the second input route information selected by the compression using a first conversion table. Then, third data consisting of both the base address and a part of the second input route information other than the part of the second input route information selected by the compression are generated, and the third data are converted to a routing tag using a second conversion table.

Abstract: An apparatus for correcting signals includes a unit for estimating distortion characteristics in high-frequency circuit portion which estimates distortion characteristics of a high-frequency circuit portion concerning amplitude distortion or phase distortion impairing linearity. The apparatus further includes an input signal processor for applying an amplitude distortion correcting function or phase distortion concerning function, which is calculated on the basis of the result of estimating the distortion characteristics, to an input signal such as low-pass signals.

Abstract: An image forming apparatus is provided for producing an array of dots in the primary scanning direction based on image data prepared for one line. The apparatus includes enlarging means for enlarging the image data n times in the primary scanning direction to form images with a resolution equal to (1/n) times a maximum resolution, where the n is a positive integer. The image forming apparatus also includes dot forming means for forming dots for n lines in the secondary scanning direction based on the enlarged image data.

Abstract: This invention is nonvolatile memory that has an ordinary memory cell region wherein ordinary data is stored and an erase information storage memory region wherein the information that shows the status of the erase operation is stored. The erase information storage memory region comprises nonvolatile memory that can store the information even when the power is cut. Preferably, the erase information storage memory region can store erase information in the memory block units in which the erase operation is executed. Further preferably, the erase information storage memory region is able to store erase information for at least the three statuses that are involved in erase operations: erase operation start status, preprogramming end status, and erase operation complete status.

Abstract: To realize a integrally constructed cooler of the heat pipe type which ensures the achievement of sufficient cooling capacity and the realization of a simple, compact and inexpensive cooler, that is especially low in height, employing and incorporating ingeniously a heat pipe, there is provided a heat pipe type cooler comprising: a heat receiving plate 3; a heat radiator having a configuration of a plurality of horizontally oriented heat radiation plates 5 extending vertically; and a heat pipe H having a generally U or V shaped profile, the middle portion of which is secured to the heat receiving plate 3: and wherein each end of the heat pipe H passes through the heat radiation plates 5.

Abstract: Disclosed herein is an error correcting apparatus for receiving a signal subjected to a repetition processing in which a part of bits of an error-correction code train are repeatedly transmitted, and decoding the received signal so as to be restored to the original data. A repetition rate calculator calculates the repetition rate of the received signal subjected to the repetition processing, a soft decision data cut-off position decision unit decides the position at which a part of the soft decision data is cut off from the soft decision data which is generated by the repetition regenerator, on the basis of the repetition rate Rr, and a bit selector cuts off the part of the soft decision data at the decided cut-off position and inputs the cut part into a soft decision error-correction decoder.

Abstract: A GALVANO-micromirror includes a first substrate having a light-reflective mirror face on one surface thereof and a first electrode on one or both surface(s) thereof; and a second substrate including a frame-form base, a second electrode located opposedly to the first electrode, a joint holder section located under the mirror face for holding the first substrate, and a torsion bar section located under the mirror face for connecting the frame-form base to the joint holder section and supporting the joint holder section pivotally within a range of angles, wherein a part of a surface of the first substrate on which the mirror face is not formed is joined to the joint holder section of the second substrate.

Abstract: A ring configuring method configures a network in which a plurality of nodes are connected linearly, and performs topology construction for the ring by circulating topology data through the respective nodes and collecting connection information of the respective nodes. The method includes the steps of providing in the topology data a flag indicating whether the connection information is collected in each node; inverting the flag at a terminal station which is an end node of the open ring, and turning the topology data there; causing the topology data to passing through a node other than any terminal station as it is; and adding the connection information to the topology data in each node according to the flag, and performing topology construction.

Abstract: A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose register as object field, on which the predetermined general-purpose arithmetic operation is to be performed by the general-purpose arithmetic operator and writes a result of the arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field. Based on the extraction and write process of the packet field designated by software (instructions), the packet processor realizes high flexibility and high speed processing.

Abstract: The semiconductor device comprises a base substrate, a wiring 54 formed on the base substrate, a first insulating film 48, 56 for covering the upper surface and the side surfaces of the wiring 54, an etching stopper film 58 formed on the base substrate and the first insulating film 48, 56, a conductor plug 36b connected to the base substrate through the etching stopper film 58 and projected upper of the base substrate, and a capacitor 79 having one electrode 68 connected to the upper surface and the side surfaces of the conductor plug 36b. The electrode 68 is formed not only on the upper surface of the conductor plug 36b but also on the side walls thereof, whereby the electrode 68 can be fixed to the conductor plug 36b without failure.